Commit 1d2091bc authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Register second AddressSpace for secure v8M CPUs 



If a v8M CPU supports the security extension then we need to
give it two AddressSpaces, the same way we do already for
an A profile core with EL3.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org
parent 1e577cc7

target/arm/cpu.c

+6 −7
Original line number Diff line number Diff line
@@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
    init_cpreg_list(cpu);



#ifndef CONFIG_USER_ONLY

    if (cpu->has_el3) {

        cs->num_ases = 2;

    } else {

        cs->num_ases = 1;

    }



    if (cpu->has_el3) {

    if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {

        AddressSpace *as;



        cs->num_ases = 2;



        if (!cpu->secure_memory) {

            cpu->secure_memory = cs->memory;

        }

        as = address_space_init_shareable(cpu->secure_memory,

                                          "cpu-secure-memory");

        cpu_address_space_init(cs, as, ARMASIdx_S);

    } else {

        cs->num_ases = 1;

    }



    cpu_address_space_init(cs,

                           address_space_init_shareable(cs->memory,

                                                        "cpu-memory"),