Commit 1cde732d authored Aug 23, 2015 by Mark Cave-Ayland Committed by Alexander Graf Sep 20, 2015

mac_dbdma: always clear FLUSH bit once DBDMA channel flush is complete



The code to flush the DBDMA channel was effectively duplicated in
dbdma_control_write(), except for the fact that the copy executed outside of a
RUN bit transition was broken by not clearing the FLUSH bit once the flush was
complete.

Newer PPC Linux kernels would timeout waiting for the FLUSH bit to clear again
after submitting a FLUSH command. Fix this by always clearing the FLUSH bit
once the channel flush is complete and removing the repeated code.

Reported-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>

parent 116dc18d

hw/misc/macio/mac_dbdma.c

+5 −7

Original line number	Diff line number	Diff line
		@@ -590,11 +590,12 @@ dbdma_control_write(DBDMA_channel *ch)
		if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
		/* RUN is cleared */
		status &= ~(ACTIVE\|DEAD);
		}

		if ((status & FLUSH) && ch->flush) {
		ch->flush(&ch->io);
		status &= ~FLUSH;
		}
		}

		DBDMA_DPRINTF(" status 0x%08x\n", status);

		@@ -603,9 +604,6 @@ dbdma_control_write(DBDMA_channel *ch)
		if (status & ACTIVE) {
		DBDMA_kick(dbdma_from_ch(ch));
		}
		if ((status & FLUSH) && ch->flush) {
		ch->flush(&ch->io);
		}
		}

		static void dbdma_write(void *opaque, hwaddr addr,