Commit 1ca74648 authored by Richard Henderson's avatar Richard Henderson
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target/hppa: Convert fp operate insns 



Tested-by: default avatarHelge Deller <deller@gmx.de>
Tested-by: default avatarSven Schnelle <svens@stackframe.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent c3bad4f8

target/hppa/insns.decode

+175 −0
Original line number Diff line number Diff line
@@ -350,3 +350,178 @@ bve 111010 b:5 00000 111 10000000000 n:1 - l=2 
fmpyfadd_f      101110 ..... ..... ... . 0 ... . . neg:1 ..... \

                rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64

fmpyfadd_d      101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5    ra3=%rc32



####

# FP operations

####



&fclass01       r t

&fclass2        r1 r2 c y

&fclass3        r1 r2 t



@f0c_0          ...... r:5  00000 ..... 00 000 0 t:5    &fclass01

@f0c_1          ...... r:5  000.. ..... 01 000 0 t:5    &fclass01

@f0c_2          ...... r1:5 r2:5 y:3 .. 10 000 . c:5    &fclass2

@f0c_3          ...... r1:5 r2:5  ..... 11 000 0 t:5    &fclass3



@f0e_f_0        ...... ..... 00000 ... 0 0 000 .. 0 .....  \

                &fclass01 r=%ra64 t=%rt64

@f0e_d_0        ...... r:5   00000 ... 0 1 000 00 0 t:5    &fclass01



@f0e_ff_1       ...... ..... 000  ... 0000 010 .. 0 .....  \

                &fclass01 r=%ra64 t=%rt64

@f0e_fd_1       ...... ..... 000  ... 0100 010 .0 0 t:5    &fclass01 r=%ra64

@f0e_df_1       ...... r:5   000  ... 0001 010 0. 0 .....  &fclass01 t=%rt64

@f0e_dd_1       ...... r:5   000  ... 0101 010 00 0 t:5    &fclass01



@f0e_f_2        ...... ..... ..... y:3 .0 100 .00 c:5      \

                &fclass2 r1=%ra64 r2=%rb64

@f0e_d_2        ...... r1:5  r2:5  y:3 01 100 000 c:5      &fclass2



@f0e_f_3        ...... ..... ..... ... .0 110 ..0 .....    \

                &fclass3 r1=%ra64 r2=%rb64 t=%rt64

@f0e_d_3        ...... r1:5  r2:5  ... 01 110 000 t:5



# Floating point class 0



# FID.  With r = t = 0, which via fcpy puts 0 into fr0.

# This is machine/revision = 0, which is reserved for simulator.

fcpy_f          001100 00000 00000 00000 000000 00000   \

                &fclass01 r=0 t=0



fcpy_f          001100 ..... ..... 010 00 ...... .....  @f0c_0

fabs_f          001100 ..... ..... 011 00 ...... .....  @f0c_0

fsqrt_f         001100 ..... ..... 100 00 ...... .....  @f0c_0

frnd_f          001100 ..... ..... 101 00 ...... .....  @f0c_0

fneg_f          001100 ..... ..... 110 00 ...... .....  @f0c_0

fnegabs_f       001100 ..... ..... 111 00 ...... .....  @f0c_0



fcpy_d          001100 ..... ..... 010 01 ...... .....  @f0c_0

fabs_d          001100 ..... ..... 011 01 ...... .....  @f0c_0

fsqrt_d         001100 ..... ..... 100 01 ...... .....  @f0c_0

frnd_d          001100 ..... ..... 101 01 ...... .....  @f0c_0

fneg_d          001100 ..... ..... 110 01 ...... .....  @f0c_0

fnegabs_d       001100 ..... ..... 111 01 ...... .....  @f0c_0



fcpy_f          001110 ..... ..... 010 ........ .....   @f0e_f_0

fabs_f          001110 ..... ..... 011 ........ .....   @f0e_f_0

fsqrt_f         001110 ..... ..... 100 ........ .....   @f0e_f_0

frnd_f          001110 ..... ..... 101 ........ .....   @f0e_f_0

fneg_f          001110 ..... ..... 110 ........ .....   @f0e_f_0

fnegabs_f       001110 ..... ..... 111 ........ .....   @f0e_f_0



fcpy_d          001110 ..... ..... 010 ........ .....   @f0e_d_0

fabs_d          001110 ..... ..... 011 ........ .....   @f0e_d_0

fsqrt_d         001110 ..... ..... 100 ........ .....   @f0e_d_0

frnd_d          001110 ..... ..... 101 ........ .....   @f0e_d_0

fneg_d          001110 ..... ..... 110 ........ .....   @f0e_d_0

fnegabs_d       001110 ..... ..... 111 ........ .....   @f0e_d_0



# Floating point class 1



# float/float

fcnv_d_f        001100 ..... ... 000 00 01 ...... ..... @f0c_1

fcnv_f_d        001100 ..... ... 000 01 00 ...... ..... @f0c_1



fcnv_d_f        001110 ..... ... 000 .......... .....   @f0e_df_1

fcnv_f_d        001110 ..... ... 000 .......... .....   @f0e_fd_1



# int/float

fcnv_w_f        001100 ..... ... 001 00 00 ...... ..... @f0c_1

fcnv_q_f        001100 ..... ... 001 00 01 ...... ..... @f0c_1

fcnv_w_d        001100 ..... ... 001 01 00 ...... ..... @f0c_1

fcnv_q_d        001100 ..... ... 001 01 01 ...... ..... @f0c_1



fcnv_w_f        001110 ..... ... 001 .......... .....   @f0e_ff_1

fcnv_q_f        001110 ..... ... 001 .......... .....   @f0e_df_1

fcnv_w_d        001110 ..... ... 001 .......... .....   @f0e_fd_1

fcnv_q_d        001110 ..... ... 001 .......... .....   @f0e_dd_1



# float/int

fcnv_f_w        001100 ..... ... 010 00 00 ...... ..... @f0c_1

fcnv_d_w        001100 ..... ... 010 00 01 ...... ..... @f0c_1

fcnv_f_q        001100 ..... ... 010 01 00 ...... ..... @f0c_1

fcnv_d_q        001100 ..... ... 010 01 01 ...... ..... @f0c_1



fcnv_f_w        001110 ..... ... 010 .......... .....   @f0e_ff_1

fcnv_d_w        001110 ..... ... 010 .......... .....   @f0e_df_1

fcnv_f_q        001110 ..... ... 010 .......... .....   @f0e_fd_1

fcnv_d_q        001110 ..... ... 010 .......... .....   @f0e_dd_1



# float/int truncate

fcnv_t_f_w      001100 ..... ... 011 00 00 ...... ..... @f0c_1

fcnv_t_d_w      001100 ..... ... 011 00 01 ...... ..... @f0c_1

fcnv_t_f_q      001100 ..... ... 011 01 00 ...... ..... @f0c_1

fcnv_t_d_q      001100 ..... ... 011 01 01 ...... ..... @f0c_1



fcnv_t_f_w      001110 ..... ... 011 .......... .....   @f0e_ff_1

fcnv_t_d_w      001110 ..... ... 011 .......... .....   @f0e_df_1

fcnv_t_f_q      001110 ..... ... 011 .......... .....   @f0e_fd_1

fcnv_t_d_q      001110 ..... ... 011 .......... .....   @f0e_dd_1



# uint/float

fcnv_uw_f       001100 ..... ... 101 00 00 ...... ..... @f0c_1

fcnv_uq_f       001100 ..... ... 101 00 01 ...... ..... @f0c_1

fcnv_uw_d       001100 ..... ... 101 01 00 ...... ..... @f0c_1

fcnv_uq_d       001100 ..... ... 101 01 01 ...... ..... @f0c_1



fcnv_uw_f       001110 ..... ... 101 .......... .....   @f0e_ff_1

fcnv_uq_f       001110 ..... ... 101 .......... .....   @f0e_df_1

fcnv_uw_d       001110 ..... ... 101 .......... .....   @f0e_fd_1

fcnv_uq_d       001110 ..... ... 101 .......... .....   @f0e_dd_1



# float/int

fcnv_f_uw       001100 ..... ... 110 00 00 ...... ..... @f0c_1

fcnv_d_uw       001100 ..... ... 110 00 01 ...... ..... @f0c_1

fcnv_f_uq       001100 ..... ... 110 01 00 ...... ..... @f0c_1

fcnv_d_uq       001100 ..... ... 110 01 01 ...... ..... @f0c_1



fcnv_f_uw       001110 ..... ... 110 .......... .....   @f0e_ff_1

fcnv_d_uw       001110 ..... ... 110 .......... .....   @f0e_df_1

fcnv_f_uq       001110 ..... ... 110 .......... .....   @f0e_fd_1

fcnv_d_uq       001110 ..... ... 110 .......... .....   @f0e_dd_1



# float/int truncate

fcnv_t_f_uw     001100 ..... ... 111 00 00 ...... ..... @f0c_1

fcnv_t_d_uw     001100 ..... ... 111 00 01 ...... ..... @f0c_1

fcnv_t_f_uq     001100 ..... ... 111 01 00 ...... ..... @f0c_1

fcnv_t_d_uq     001100 ..... ... 111 01 01 ...... ..... @f0c_1



fcnv_t_f_uw     001110 ..... ... 111 .......... .....   @f0e_ff_1

fcnv_t_d_uw     001110 ..... ... 111 .......... .....   @f0e_df_1

fcnv_t_f_uq     001110 ..... ... 111 .......... .....   @f0e_fd_1

fcnv_t_d_uq     001110 ..... ... 111 .......... .....   @f0e_dd_1



# Floating point class 2



ftest           001100 00000 00000 y:3 00 10000 1 c:5



fcmp_f          001100 ..... ..... ... 00 ..... 0 ..... @f0c_2

fcmp_d          001100 ..... ..... ... 01 ..... 0 ..... @f0c_2



fcmp_f          001110 ..... ..... ... ..... ... .....  @f0e_f_2

fcmp_d          001110 ..... ..... ... ..... ... .....  @f0e_d_2



# Floating point class 3



fadd_f          001100 ..... ..... 000 00 ...... .....  @f0c_3

fsub_f          001100 ..... ..... 001 00 ...... .....  @f0c_3

fmpy_f          001100 ..... ..... 010 00 ...... .....  @f0c_3

fdiv_f          001100 ..... ..... 011 00 ...... .....  @f0c_3



fadd_d          001100 ..... ..... 000 01 ...... .....  @f0c_3

fsub_d          001100 ..... ..... 001 01 ...... .....  @f0c_3

fmpy_d          001100 ..... ..... 010 01 ...... .....  @f0c_3

fdiv_d          001100 ..... ..... 011 01 ...... .....  @f0c_3



fadd_f          001110 ..... ..... 000 ..... ... .....  @f0e_f_3

fsub_f          001110 ..... ..... 001 ..... ... .....  @f0e_f_3

fmpy_f          001110 ..... ..... 010 ..... ... .....  @f0e_f_3

fdiv_f          001110 ..... ..... 011 ..... ... .....  @f0e_f_3



fadd_d          001110 ..... ..... 000 ..... ... .....  @f0e_d_3

fsub_d          001110 ..... ..... 001 ..... ... .....  @f0e_d_3

fmpy_d          001110 ..... ..... 010 ..... ... .....  @f0e_d_3

fdiv_d          001110 ..... ..... 011 ..... ... .....  @f0e_d_3



xmpyu           001110 ..... ..... 010 .0111 .00 t:5    r1=%ra64 r2=%rb64

target/hppa/translate.c

+308 −435

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