Commit 1bcea73e authored by Lluís Vilanova's avatar Lluís Vilanova Committed by Stefan Hajnoczi
Browse files

tcg: Add type for vCPU pointers 



Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The
tracing infrastructure later needs to differentiate between regular
pointers and pointers to vCPUs.

Also changes all targets to use the new 'TCGv_env' type instead of the
generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env'
translates into 'TCGv_ptr'), but that could change in the future to
enforce the difference.

Note that a 'TCGv_env' type (for 'CPUState') is not added, since all
helpers currently receive the architecture-specific
pointer ('CPUArchState').

Signed-off-by: default avatarLluís Vilanova <vilanova@ac.upc.edu>
Acked-by: default avatarRichard Henderson <rth@twiddle.net>
Message-id: 145641859552.30295.7821536833590725201.stgit@localhost
Signed-off-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
parent 56797b1f

target-alpha/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ typedef enum { 
} ExitStatus;



/* global register indexes */

static TCGv_ptr cpu_env;

static TCGv_env cpu_env;

static TCGv cpu_std_ir[31];

static TCGv cpu_fir[31];

static TCGv cpu_pc;

target-arm/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ 
#define IS_USER(s) (s->user)

#endif



TCGv_ptr cpu_env;

TCGv_env cpu_env;

/* We reuse the same 64-bit temporaries for efficiency.  */

static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;

static TCGv_i32 cpu_R[16];

target-arm/translate.h

+1 −1
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ typedef struct DisasCompare { 
} DisasCompare;



/* Share the TCG temporaries common between 32 and 64 bit modes.  */

extern TCGv_ptr cpu_env;

extern TCGv_env cpu_env;

extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;

extern TCGv_i64 cpu_exclusive_addr;

extern TCGv_i64 cpu_exclusive_val;

target-cris/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ 
#define CC_MASK_NZVC 0xf

#define CC_MASK_RNZV 0x10e



static TCGv_ptr cpu_env;

static TCGv_env cpu_env;

static TCGv cpu_R[16];

static TCGv cpu_PR[16];

static TCGv cc_x;

target-i386/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ 
//#define MACRO_TEST   1



/* global register indexes */

static TCGv_ptr cpu_env;

static TCGv_env cpu_env;

static TCGv cpu_A0;

static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2, cpu_cc_srcT;

static TCGv_i32 cpu_cc_op;