Commit 1bbe5dc6 authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170228' into staging 



target-arm queue:
 * raspi2: implement RNG module
 * raspi2: implement new SD card controller (but don't wire it up)
 * sdhci: bugfixes for block transfers
 * virt: fix cpu object reference leak
 * Add missing fp_access_check() to aarch64 crypto instructions
 * cputlb: Don't assume do_unassigned_access() never returns
 * virt: Add a user option to disallow ITS instantiation
 * i.MX timers: fix reset handling
 * ARMv7M NVIC: rewrite to fix broken priority handling and masking
 * exynos: Fix proper mapping of CPUs by providing real cluster ID
 * exynos: Fix Linux kernel division by zero for PLLs

# gpg: Signature made Tue 28 Feb 2017 12:40:51 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170228: (27 commits)
  hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID
  hw/arm/exynos: Fix Linux kernel division by zero for PLLs
  bcm2835_sdhost: add bcm2835 sdhost controller
  armv7m: Allow SHCSR writes to change pending and active bits
  armv7m: Raise correct kind of UsageFault for attempts to execute ARM code
  armv7m: Check exception return consistency
  armv7m: Extract "exception taken" code into functions
  armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE
  armv7m: Simpler and faster exception start
  armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value
  armv7m: Escalate exceptions to HardFault if necessary
  arm: gic: Remove references to NVIC
  armv7m: Fix condition check for taking exceptions
  armv7m: Rewrite NVIC to not use any GIC code
  armv7m: Implement reading and writing of PRIGROUP
  armv7m: Rename nvic_state to NVICState
  ARM i.MX timers: fix reset handling
  hw/arm/virt: Add a user option to disallow ITS instantiation
  cputlb: Don't assume do_unassigned_access() never returns
  Add missing fp_access_check() to aarch64 crypto instructions
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c8c0a1a7 f3a6339a

cputlb.c

+7 −8
Original line number Diff line number Diff line
@@ -769,15 +769,14 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 
    pd = iotlbentry->addr & ~TARGET_PAGE_MASK;

    mr = iotlb_to_region(cpu, pd, iotlbentry->attrs);

    if (memory_region_is_unassigned(mr)) {

        CPUClass *cc = CPU_GET_CLASS(cpu);



        if (cc->do_unassigned_access) {

            cc->do_unassigned_access(cpu, addr, false, true, 0, 4);

        } else {

        cpu_unassigned_access(cpu, addr, false, true, 0, 4);

        /* The CPU's unassigned access hook might have longjumped out

         * with an exception. If it didn't (or there was no hook) then

         * we can't proceed further.

         */

        report_bad_exec(cpu, addr);

        exit(1);

    }

    }

    p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);

    return qemu_ram_addr_from_host_nofail(p);

}

hw/arm/bcm2835_peripherals.c

+15 −0
Original line number Diff line number Diff line
@@ -86,6 +86,11 @@ static void bcm2835_peripherals_init(Object *obj) 
    object_property_add_const_link(OBJECT(&s->property), "dma-mr",

                                   OBJECT(&s->gpu_bus_mr), &error_abort);



    /* Random Number Generator */

    object_initialize(&s->rng, sizeof(s->rng), TYPE_BCM2835_RNG);

    object_property_add_child(obj, "rng", OBJECT(&s->rng), NULL);

    qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default());



    /* Extended Mass Media Controller */

    object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI);

    object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
@@ -226,6 +231,16 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) 
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,

                      qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));



    /* Random Number Generator */

    object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    memory_region_add_subregion(&s->peri_mr, RNG_OFFSET,

                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0));



    /* Extended Mass Media Controller */

    object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",

                            &err);

hw/arm/exynos4210.c

+18 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "qemu/osdep.h"

#include "qapi/error.h"

#include "qemu-common.h"

#include "qemu/log.h"

#include "cpu.h"

#include "hw/boards.h"

#include "sysemu/sysemu.h"
@@ -74,6 +75,9 @@ 
/* PMU SFR base address */

#define EXYNOS4210_PMU_BASE_ADDR            0x10020000



/* Clock controller SFR base address */

#define EXYNOS4210_CLK_BASE_ADDR            0x10030000



/* Display controllers (FIMD) */

#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
@@ -138,6 +142,16 @@ void exynos4210_write_secondary(ARMCPU *cpu, 
                       info->smp_loader_start);

}



static uint64_t exynos4210_calc_affinity(int cpu)

{

    uint64_t mp_affinity;



    /* Exynos4210 has 0x9 as cluster ID */

    mp_affinity = (0x9 << ARM_AFF1_SHIFT) | cpu;



    return mp_affinity;

}



Exynos4210State *exynos4210_init(MemoryRegion *system_mem,

        unsigned long ram_size)

{
@@ -163,6 +177,8 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 
        }



        s->cpu[n] = ARM_CPU(cpuobj);

        object_property_set_int(cpuobj, exynos4210_calc_affinity(n),

                                "mp-affinity", &error_abort);

        object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,

                                "reset-cbar", &error_abort);

        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
@@ -297,6 +313,8 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, 
    */

    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);



    sysbus_create_simple("exynos4210.clk", EXYNOS4210_CLK_BASE_ADDR, NULL);



    /* PWM */

    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,

                          s->irq_table[exynos4210_get_irq(22, 0)],

hw/arm/virt.c

+30 −2
Original line number Diff line number Diff line
@@ -535,7 +535,6 @@ static void create_v2m(VirtMachineState *vms, qemu_irq *pic) 
static void create_gic(VirtMachineState *vms, qemu_irq *pic)

{

    /* We create a standalone GIC */

    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);

    DeviceState *gicdev;

    SysBusDevice *gicbusdev;

    const char *gictype;
@@ -605,7 +604,7 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) 


    fdt_add_gic_node(vms);



    if (type == 3 && !vmc->no_its) {

    if (type == 3 && vms->its) {

        create_its(vms, gicdev);

    } else if (type == 2) {

        create_v2m(vms, pic);
@@ -1378,6 +1377,7 @@ static void machvirt_init(MachineState *machine) 
        }



        object_property_set_bool(cpuobj, true, "realized", NULL);

        object_unref(cpuobj);

    }

    fdt_add_timer_nodes(vms);

    fdt_add_cpu_nodes(vms);
@@ -1480,6 +1480,20 @@ static void virt_set_highmem(Object *obj, bool value, Error **errp) 
    vms->highmem = value;

}



static bool virt_get_its(Object *obj, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);



    return vms->its;

}



static void virt_set_its(Object *obj, bool value, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);



    vms->its = value;

}



static char *virt_get_gic_version(Object *obj, Error **errp)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1540,6 +1554,7 @@ type_init(machvirt_machine_init); 
static void virt_2_9_instance_init(Object *obj)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);

    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);



    /* EL3 is disabled by default on virt: this makes us consistent

     * between KVM and TCG for this board, and it also allows us to
@@ -1579,6 +1594,19 @@ static void virt_2_9_instance_init(Object *obj) 
                                    "Set GIC version. "

                                    "Valid values are 2, 3 and host", NULL);



    if (vmc->no_its) {

        vms->its = false;

    } else {

        /* Default allows ITS instantiation */

        vms->its = true;

        object_property_add_bool(obj, "its", virt_get_its,

                                 virt_set_its, NULL);

        object_property_set_description(obj, "its",

                                        "Set on/off to enable/disable "

                                        "ITS instantiation",

                                        NULL);

    }



    vms->memmap = a15memmap;

    vms->irqmap = a15irqmap;

}

hw/intc/arm_gic.c

+5 −26
Original line number Diff line number Diff line
@@ -156,17 +156,6 @@ static void gic_set_irq_11mpcore(GICState *s, int irq, int level, 
    }

}



static void gic_set_irq_nvic(GICState *s, int irq, int level,

                                 int cm, int target)

{

    if (level) {

        GIC_SET_LEVEL(irq, cm);

        GIC_SET_PENDING(irq, target);

    } else {

        GIC_CLEAR_LEVEL(irq, cm);

    }

}



static void gic_set_irq_generic(GICState *s, int irq, int level,

                                int cm, int target)

{
@@ -214,8 +203,6 @@ static void gic_set_irq(void *opaque, int irq, int level) 


    if (s->revision == REV_11MPCORE) {

        gic_set_irq_11mpcore(s, irq, level, cm, target);

    } else if (s->revision == REV_NVIC) {

        gic_set_irq_nvic(s, irq, level, cm, target);

    } else {

        gic_set_irq_generic(s, irq, level, cm, target);

    }
@@ -367,7 +354,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) 
        return 1023;

    }



    if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {

    if (s->revision == REV_11MPCORE) {

        /* Clear pending flags for both level and edge triggered interrupts.

         * Level triggered IRQs will be reasserted once they become inactive.

         */
@@ -589,11 +576,6 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) 
            DPRINTF("Set %d pending mask %x\n", irq, cm);

            GIC_SET_PENDING(irq, cm);

        }

    } else if (s->revision == REV_NVIC) {

        if (GIC_TEST_LEVEL(irq, cm)) {

            DPRINTF("Set nvic %d pending mask %x\n", irq, cm);

            GIC_SET_PENDING(irq, cm);

        }

    }



    group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
@@ -768,7 +750,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 
    } else if (offset < 0xf10) {

        goto bad_reg;

    } else if (offset < 0xf30) {

        if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {

        if (s->revision == REV_11MPCORE) {

            goto bad_reg;

        }
@@ -802,9 +784,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) 
            case 2:

                res = gic_id_gicv2[(offset - 0xfd0) >> 2];

                break;

            case REV_NVIC:

                /* Shouldn't be able to get here */

                abort();

            default:

                res = 0;

            }
@@ -1028,7 +1007,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, 
                continue; /* Ignore Non-secure access of Group0 IRQ */

            }



            if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {

            if (s->revision == REV_11MPCORE) {

                if (value & (1 << (i * 2))) {

                    GIC_SET_MODEL(irq + i);

                } else {
@@ -1046,7 +1025,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, 
        goto bad_reg;

    } else if (offset < 0xf20) {

        /* GICD_CPENDSGIRn */

        if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {

        if (s->revision == REV_11MPCORE) {

            goto bad_reg;

        }

        irq = (offset - 0xf10);
@@ -1060,7 +1039,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, 
        }

    } else if (offset < 0xf30) {

        /* GICD_SPENDSGIRn */

        if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {

        if (s->revision == REV_11MPCORE) {

            goto bad_reg;

        }

        irq = (offset - 0xf20);