Commit 1b756f1a authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160701' into staging 



ppc patch queue 2016-07-01

Here's the current ppc patch queue.  This is a fairly large batch,
containing:
    * A number of further preliminary patches towards full hypervisor
      mode emulation
    * Some further fixes / cleanups for the recently merged device_add
      based CPU hotplug
    * Preliminary patches towards supporting a native (rather than
      paravirtualized) XICS device.  This will be needed to emulate a
      physical Power machine, including hypervisor capabilities
    * Assorted bug fixes

# gpg: Signature made Fri 01 Jul 2016 06:56:35 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.7-20160701: (23 commits)
  qmp: fix spapr example of query-hotpluggable-cpus
  spapr: drop duplicate variable in spapr_core_release()
  spapr: do proper error propagation in spapr_cpu_core_realize_child()
  spapr: drop reference on child object during core realization
  spapr: Restore support for 970MP and POWER8NVL CPU cores
  target-ppc: gen_pause for instructions: yield, mdoio, mdoom, miso
  ppc/xics: Replace "icp" with "xics" in most places
  ppc/xics: Implement H_IPOLL using an accessor
  ppc/xics: Move SPAPR specific code to a separate file
  ppc/xics: Rename existing xics to xics_spapr
  ppc: Fix 64K pages support in full emulation
  target-ppc: Eliminate redundant and incorrect function booke206_page_size_to_tlb
  spapr: Restore support for older PowerPC CPU cores
  spapr: fix write-past-end-of-array error in cpu core device init code
  hw/ppc/spapr: Add some missing hcall function set strings
  ppc: Print HSRR0/HSRR1 in "info registers"
  ppc: LPCR is a HV resource
  ppc: Initial HDEC support
  ppc: Enforce setting MSR:EE,IR and DR when MSR:PR is set
  ppc: Fix conditions for delivering external interrupts to a guest
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 94e31093 13f5e800

default-configs/ppc64-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ CONFIG_ETSEC=y 
CONFIG_LIBDECNUMBER=y

# For pSeries

CONFIG_XICS=$(CONFIG_PSERIES)

CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)

CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))

# For PReP

CONFIG_MC146818RTC=y

hw/intc/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o 
obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o

obj-$(CONFIG_SH4) += sh_intc.o

obj-$(CONFIG_XICS) += xics.o

obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o

obj-$(CONFIG_XICS_KVM) += xics_kvm.o

obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o

obj-$(CONFIG_S390_FLIC) += s390_flic.o

hw/intc/xics.c

+73 −464
Original line number Diff line number Diff line
@@ -32,12 +32,11 @@ 
#include "hw/hw.h"

#include "trace.h"

#include "qemu/timer.h"

#include "hw/ppc/spapr.h"

#include "hw/ppc/xics.h"

#include "qemu/error-report.h"

#include "qapi/visitor.h"



static int get_cpu_index_by_dt_id(int cpu_dt_id)

int xics_get_cpu_index_by_dt_id(int cpu_dt_id)

{

    PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
@@ -48,31 +47,31 @@ static int get_cpu_index_by_dt_id(int cpu_dt_id) 
    return -1;

}



void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu)

void xics_cpu_destroy(XICSState *xics, PowerPCCPU *cpu)

{

    CPUState *cs = CPU(cpu);

    ICPState *ss = &icp->ss[cs->cpu_index];

    ICPState *ss = &xics->ss[cs->cpu_index];



    assert(cs->cpu_index < icp->nr_servers);

    assert(cs->cpu_index < xics->nr_servers);

    assert(cs == ss->cs);



    ss->output = NULL;

    ss->cs = NULL;

}



void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)

void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)

{

    CPUState *cs = CPU(cpu);

    CPUPPCState *env = &cpu->env;

    ICPState *ss = &icp->ss[cs->cpu_index];

    XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);

    ICPState *ss = &xics->ss[cs->cpu_index];

    XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);



    assert(cs->cpu_index < icp->nr_servers);

    assert(cs->cpu_index < xics->nr_servers);



    ss->cs = cs;



    if (info->cpu_setup) {

        info->cpu_setup(icp, cpu);

        info->cpu_setup(xics, cpu);

    }



    switch (PPC_INPUT(env)) {
@@ -96,21 +95,21 @@ void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) 
 */

static void xics_common_reset(DeviceState *d)

{

    XICSState *icp = XICS_COMMON(d);

    XICSState *xics = XICS_COMMON(d);

    int i;



    for (i = 0; i < icp->nr_servers; i++) {

        device_reset(DEVICE(&icp->ss[i]));

    for (i = 0; i < xics->nr_servers; i++) {

        device_reset(DEVICE(&xics->ss[i]));

    }



    device_reset(DEVICE(icp->ics));

    device_reset(DEVICE(xics->ics));

}



static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,

                                  void *opaque, Error **errp)

{

    XICSState *icp = XICS_COMMON(obj);

    int64_t value = icp->nr_irqs;

    XICSState *xics = XICS_COMMON(obj);

    int64_t value = xics->nr_irqs;



    visit_type_int(v, name, &value, errp);

}
@@ -118,8 +117,8 @@ static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name, 
static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,

                                  void *opaque, Error **errp)

{

    XICSState *icp = XICS_COMMON(obj);

    XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);

    XICSState *xics = XICS_COMMON(obj);

    XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);

    Error *error = NULL;

    int64_t value;
@@ -128,23 +127,23 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name, 
        error_propagate(errp, error);

        return;

    }

    if (icp->nr_irqs) {

    if (xics->nr_irqs) {

        error_setg(errp, "Number of interrupts is already set to %u",

                   icp->nr_irqs);

                   xics->nr_irqs);

        return;

    }



    assert(info->set_nr_irqs);

    assert(icp->ics);

    info->set_nr_irqs(icp, value, errp);

    assert(xics->ics);

    info->set_nr_irqs(xics, value, errp);

}



static void xics_prop_get_nr_servers(Object *obj, Visitor *v,

                                     const char *name, void *opaque,

                                     Error **errp)

{

    XICSState *icp = XICS_COMMON(obj);

    int64_t value = icp->nr_servers;

    XICSState *xics = XICS_COMMON(obj);

    int64_t value = xics->nr_servers;



    visit_type_int(v, name, &value, errp);

}
@@ -153,8 +152,8 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v, 
                                     const char *name, void *opaque,

                                     Error **errp)

{

    XICSState *icp = XICS_COMMON(obj);

    XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);

    XICSState *xics = XICS_COMMON(obj);

    XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);

    Error *error = NULL;

    int64_t value;
@@ -163,14 +162,14 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v, 
        error_propagate(errp, error);

        return;

    }

    if (icp->nr_servers) {

    if (xics->nr_servers) {

        error_setg(errp, "Number of servers is already set to %u",

                   icp->nr_servers);

                   xics->nr_servers);

        return;

    }



    assert(info->set_nr_servers);

    info->set_nr_servers(icp, value, errp);

    info->set_nr_servers(xics, value, errp);

}



static void xics_common_initfn(Object *obj)
@@ -213,9 +212,9 @@ static void ics_reject(ICSState *ics, int nr); 
static void ics_resend(ICSState *ics);

static void ics_eoi(ICSState *ics, int nr);



static void icp_check_ipi(XICSState *icp, int server)

static void icp_check_ipi(XICSState *xics, int server)

{

    ICPState *ss = icp->ss + server;

    ICPState *ss = xics->ss + server;



    if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {

        return;
@@ -224,7 +223,7 @@ static void icp_check_ipi(XICSState *icp, int server) 
    trace_xics_icp_check_ipi(server, ss->mfrr);



    if (XISR(ss)) {

        ics_reject(icp->ics, XISR(ss));

        ics_reject(xics->ics, XISR(ss));

    }



    ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
@@ -232,19 +231,19 @@ static void icp_check_ipi(XICSState *icp, int server) 
    qemu_irq_raise(ss->output);

}



static void icp_resend(XICSState *icp, int server)

static void icp_resend(XICSState *xics, int server)

{

    ICPState *ss = icp->ss + server;

    ICPState *ss = xics->ss + server;



    if (ss->mfrr < CPPR(ss)) {

        icp_check_ipi(icp, server);

        icp_check_ipi(xics, server);

    }

    ics_resend(icp->ics);

    ics_resend(xics->ics);

}



static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)

void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)

{

    ICPState *ss = icp->ss + server;

    ICPState *ss = xics->ss + server;

    uint8_t old_cppr;

    uint32_t old_xisr;
@@ -257,26 +256,26 @@ static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) 
            ss->xirr &= ~XISR_MASK; /* Clear XISR */

            ss->pending_priority = 0xff;

            qemu_irq_lower(ss->output);

            ics_reject(icp->ics, old_xisr);

            ics_reject(xics->ics, old_xisr);

        }

    } else {

        if (!XISR(ss)) {

            icp_resend(icp, server);

            icp_resend(xics, server);

        }

    }

}



static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)

void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)

{

    ICPState *ss = icp->ss + server;

    ICPState *ss = xics->ss + server;



    ss->mfrr = mfrr;

    if (mfrr < CPPR(ss)) {

        icp_check_ipi(icp, server);

        icp_check_ipi(xics, server);

    }

}



static uint32_t icp_accept(ICPState *ss)

uint32_t icp_accept(ICPState *ss)

{

    uint32_t xirr = ss->xirr;
@@ -289,31 +288,39 @@ static uint32_t icp_accept(ICPState *ss) 
    return xirr;

}



static void icp_eoi(XICSState *icp, int server, uint32_t xirr)

uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)

{

    ICPState *ss = icp->ss + server;

    if (mfrr) {

        *mfrr = ss->mfrr;

    }

    return ss->xirr;

}



void icp_eoi(XICSState *xics, int server, uint32_t xirr)

{

    ICPState *ss = xics->ss + server;



    /* Send EOI -> ICS */

    ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);

    trace_xics_icp_eoi(server, xirr, ss->xirr);

    ics_eoi(icp->ics, xirr & XISR_MASK);

    ics_eoi(xics->ics, xirr & XISR_MASK);

    if (!XISR(ss)) {

        icp_resend(icp, server);

        icp_resend(xics, server);

    }

}



static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)

static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)

{

    ICPState *ss = icp->ss + server;

    ICPState *ss = xics->ss + server;



    trace_xics_icp_irq(server, nr, priority);



    if ((priority >= CPPR(ss))

        || (XISR(ss) && (ss->pending_priority <= priority))) {

        ics_reject(icp->ics, nr);

        ics_reject(xics->ics, nr);

    } else {

        if (XISR(ss)) {

            ics_reject(icp->ics, XISR(ss));

            ics_reject(xics->ics, XISR(ss));

        }

        ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);

        ss->pending_priority = priority;
@@ -390,12 +397,6 @@ static const TypeInfo icp_info = { 
/*

 * ICS: Source layer

 */

static int ics_valid_irq(ICSState *ics, uint32_t nr)

{

    return (nr >= ics->offset)

        && (nr < (ics->offset + ics->nr_irqs));

}



static void resend_msi(ICSState *ics, int srcno)

{

    ICSIRQState *irq = ics->irqs + srcno;
@@ -404,7 +405,7 @@ static void resend_msi(ICSState *ics, int srcno) 
    if (irq->status & XICS_STATUS_REJECTED) {

        irq->status &= ~XICS_STATUS_REJECTED;

        if (irq->priority != 0xff) {

            icp_irq(ics->icp, irq->server, srcno + ics->offset,

            icp_irq(ics->xics, irq->server, srcno + ics->offset,

                    irq->priority);

        }

    }
@@ -418,7 +419,7 @@ static void resend_lsi(ICSState *ics, int srcno) 
        && (irq->status & XICS_STATUS_ASSERTED)

        && !(irq->status & XICS_STATUS_SENT)) {

        irq->status |= XICS_STATUS_SENT;

        icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);

        icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);

    }

}
@@ -433,7 +434,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val) 
            irq->status |= XICS_STATUS_MASKED_PENDING;

            trace_xics_masked_pending();

        } else  {

            icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);

            icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);

        }

    }

}
@@ -472,7 +473,7 @@ static void write_xive_msi(ICSState *ics, int srcno) 
    }



    irq->status &= ~XICS_STATUS_MASKED_PENDING;

    icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);

    icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);

}



static void write_xive_lsi(ICSState *ics, int srcno)
@@ -480,7 +481,7 @@ static void write_xive_lsi(ICSState *ics, int srcno) 
    resend_lsi(ics, srcno);

}



static void ics_write_xive(ICSState *ics, int nr, int server,

void ics_write_xive(ICSState *ics, int nr, int server,

                    uint8_t priority, uint8_t saved_priority)

{

    int srcno = nr - ics->offset;
@@ -557,8 +558,8 @@ static int ics_post_load(ICSState *ics, int version_id) 
{

    int i;



    for (i = 0; i < ics->icp->nr_servers; i++) {

        icp_resend(ics->icp, i);

    for (i = 0; i < ics->xics->nr_servers; i++) {

        icp_resend(ics->xics, i);

    }



    return 0;
@@ -658,14 +659,14 @@ static const TypeInfo ics_info = { 
/*

 * Exported functions

 */

static int xics_find_source(XICSState *icp, int irq)

int xics_find_source(XICSState *xics, int irq)

{

    int sources = 1;

    int src;



    /* FIXME: implement multiple sources */

    for (src = 0; src < sources; ++src) {

        ICSState *ics = &icp->ics[src];

        ICSState *ics = &xics->ics[src];

        if (ics_valid_irq(ics, irq)) {

            return src;

        }
@@ -674,19 +675,19 @@ static int xics_find_source(XICSState *icp, int irq) 
    return -1;

}



qemu_irq xics_get_qirq(XICSState *icp, int irq)

qemu_irq xics_get_qirq(XICSState *xics, int irq)

{

    int src = xics_find_source(icp, irq);

    int src = xics_find_source(xics, irq);



    if (src >= 0) {

        ICSState *ics = &icp->ics[src];

        ICSState *ics = &xics->ics[src];

        return ics->qirqs[irq - ics->offset];

    }



    return NULL;

}



static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)

void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)

{

    assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
@@ -694,401 +695,9 @@ static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) 
        lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;

}



#define ICS_IRQ_FREE(ics, srcno)   \

    (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))



static int ics_find_free_block(ICSState *ics, int num, int alignnum)

{

    int first, i;



    for (first = 0; first < ics->nr_irqs; first += alignnum) {

        if (num > (ics->nr_irqs - first)) {

            return -1;

        }

        for (i = first; i < first + num; ++i) {

            if (!ICS_IRQ_FREE(ics, i)) {

                break;

            }

        }

        if (i == (first + num)) {

            return first;

        }

    }



    return -1;

}



int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)

{

    ICSState *ics = &icp->ics[src];

    int irq;



    if (irq_hint) {

        assert(src == xics_find_source(icp, irq_hint));

        if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {

            error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);

            return -1;

        }

        irq = irq_hint;

    } else {

        irq = ics_find_free_block(ics, 1, 1);

        if (irq < 0) {

            error_setg(errp, "can't allocate IRQ: no IRQ left");

            return -1;

        }

        irq += ics->offset;

    }



    ics_set_irq_type(ics, irq - ics->offset, lsi);

    trace_xics_alloc(src, irq);



    return irq;

}



/*

 * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.

 * If align==true, aligns the first IRQ number to num.

 */

int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,

                     Error **errp)

{

    int i, first = -1;

    ICSState *ics = &icp->ics[src];



    assert(src == 0);

    /*

     * MSIMesage::data is used for storing VIRQ so

     * it has to be aligned to num to support multiple

     * MSI vectors. MSI-X is not affected by this.

     * The hint is used for the first IRQ, the rest should

     * be allocated continuously.

     */

    if (align) {

        assert((num == 1) || (num == 2) || (num == 4) ||

               (num == 8) || (num == 16) || (num == 32));

        first = ics_find_free_block(ics, num, num);

    } else {

        first = ics_find_free_block(ics, num, 1);

    }

    if (first < 0) {

        error_setg(errp, "can't find a free %d-IRQ block", num);

        return -1;

    }



    if (first >= 0) {

        for (i = first; i < first + num; ++i) {

            ics_set_irq_type(ics, i, lsi);

        }

    }

    first += ics->offset;



    trace_xics_alloc_block(src, first, num, lsi, align);



    return first;

}



static void ics_free(ICSState *ics, int srcno, int num)

{

    int i;



    for (i = srcno; i < srcno + num; ++i) {

        if (ICS_IRQ_FREE(ics, i)) {

            trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);

        }

        memset(&ics->irqs[i], 0, sizeof(ICSIRQState));

    }

}



void xics_free(XICSState *icp, int irq, int num)

{

    int src = xics_find_source(icp, irq);



    if (src >= 0) {

        ICSState *ics = &icp->ics[src];



        /* FIXME: implement multiple sources */

        assert(src == 0);



        trace_xics_ics_free(ics - icp->ics, irq, num);

        ics_free(ics, irq - ics->offset, num);

    }

}



/*

 * Guest interfaces

 */



static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                           target_ulong opcode, target_ulong *args)

{

    CPUState *cs = CPU(cpu);

    target_ulong cppr = args[0];



    icp_set_cppr(spapr->icp, cs->cpu_index, cppr);

    return H_SUCCESS;

}



static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                          target_ulong opcode, target_ulong *args)

{

    target_ulong server = get_cpu_index_by_dt_id(args[0]);

    target_ulong mfrr = args[1];



    if (server >= spapr->icp->nr_servers) {

        return H_PARAMETER;

    }



    icp_set_mfrr(spapr->icp, server, mfrr);

    return H_SUCCESS;

}



static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                           target_ulong opcode, target_ulong *args)

{

    CPUState *cs = CPU(cpu);

    uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);



    args[0] = xirr;

    return H_SUCCESS;

}



static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                             target_ulong opcode, target_ulong *args)

{

    CPUState *cs = CPU(cpu);

    ICPState *ss = &spapr->icp->ss[cs->cpu_index];

    uint32_t xirr = icp_accept(ss);



    args[0] = xirr;

    args[1] = cpu_get_host_ticks();

    return H_SUCCESS;

}



static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                          target_ulong opcode, target_ulong *args)

{

    CPUState *cs = CPU(cpu);

    target_ulong xirr = args[0];



    icp_eoi(spapr->icp, cs->cpu_index, xirr);

    return H_SUCCESS;

}



static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                            target_ulong opcode, target_ulong *args)

{

    CPUState *cs = CPU(cpu);

    ICPState *ss = &spapr->icp->ss[cs->cpu_index];



    args[0] = ss->xirr;

    args[1] = ss->mfrr;



    return H_SUCCESS;

}



static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                          uint32_t token,

                          uint32_t nargs, target_ulong args,

                          uint32_t nret, target_ulong rets)

{

    ICSState *ics = spapr->icp->ics;

    uint32_t nr, server, priority;



    if ((nargs != 3) || (nret != 1)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    nr = rtas_ld(args, 0);

    server = get_cpu_index_by_dt_id(rtas_ld(args, 1));

    priority = rtas_ld(args, 2);



    if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)

        || (priority > 0xff)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    ics_write_xive(ics, nr, server, priority, priority);



    rtas_st(rets, 0, RTAS_OUT_SUCCESS);

}



static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                          uint32_t token,

                          uint32_t nargs, target_ulong args,

                          uint32_t nret, target_ulong rets)

{

    ICSState *ics = spapr->icp->ics;

    uint32_t nr;



    if ((nargs != 1) || (nret != 3)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    nr = rtas_ld(args, 0);



    if (!ics_valid_irq(ics, nr)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    rtas_st(rets, 0, RTAS_OUT_SUCCESS);

    rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);

    rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);

}



static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                         uint32_t token,

                         uint32_t nargs, target_ulong args,

                         uint32_t nret, target_ulong rets)

{

    ICSState *ics = spapr->icp->ics;

    uint32_t nr;



    if ((nargs != 1) || (nret != 1)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    nr = rtas_ld(args, 0);



    if (!ics_valid_irq(ics, nr)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,

                   ics->irqs[nr - ics->offset].priority);



    rtas_st(rets, 0, RTAS_OUT_SUCCESS);

}



static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,

                        uint32_t token,

                        uint32_t nargs, target_ulong args,

                        uint32_t nret, target_ulong rets)

{

    ICSState *ics = spapr->icp->ics;

    uint32_t nr;



    if ((nargs != 1) || (nret != 1)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    nr = rtas_ld(args, 0);



    if (!ics_valid_irq(ics, nr)) {

        rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);

        return;

    }



    ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,

                   ics->irqs[nr - ics->offset].saved_priority,

                   ics->irqs[nr - ics->offset].saved_priority);



    rtas_st(rets, 0, RTAS_OUT_SUCCESS);

}



/*

 * XICS

 */



static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)

{

    icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;

}



static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,

                                Error **errp)

{

    int i;



    icp->nr_servers = nr_servers;



    icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));

    for (i = 0; i < icp->nr_servers; i++) {

        char buffer[32];

        object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);

        snprintf(buffer, sizeof(buffer), "icp[%d]", i);

        object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),

                                  errp);

    }

}



static void xics_realize(DeviceState *dev, Error **errp)

{

    XICSState *icp = XICS(dev);

    Error *error = NULL;

    int i;



    if (!icp->nr_servers) {

        error_setg(errp, "Number of servers needs to be greater 0");

        return;

    }



    /* Registration of global state belongs into realize */

    spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);

    spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);

    spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);

    spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);



    spapr_register_hypercall(H_CPPR, h_cppr);

    spapr_register_hypercall(H_IPI, h_ipi);

    spapr_register_hypercall(H_XIRR, h_xirr);

    spapr_register_hypercall(H_XIRR_X, h_xirr_x);

    spapr_register_hypercall(H_EOI, h_eoi);

    spapr_register_hypercall(H_IPOLL, h_ipoll);



    object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);

    if (error) {

        error_propagate(errp, error);

        return;

    }



    for (i = 0; i < icp->nr_servers; i++) {

        object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);

        if (error) {

            error_propagate(errp, error);

            return;

        }

    }

}



static void xics_initfn(Object *obj)

{

    XICSState *xics = XICS(obj);



    xics->ics = ICS(object_new(TYPE_ICS));

    object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);

    xics->ics->icp = xics;

}



static void xics_class_init(ObjectClass *oc, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(oc);

    XICSStateClass *xsc = XICS_CLASS(oc);



    dc->realize = xics_realize;

    xsc->set_nr_irqs = xics_set_nr_irqs;

    xsc->set_nr_servers = xics_set_nr_servers;

}



static const TypeInfo xics_info = {

    .name          = TYPE_XICS,

    .parent        = TYPE_XICS_COMMON,

    .instance_size = sizeof(XICSState),

    .class_size = sizeof(XICSStateClass),

    .class_init    = xics_class_init,

    .instance_init = xics_initfn,

};



static void xics_register_types(void)

{

    type_register_static(&xics_common_info);

    type_register_static(&xics_info);

    type_register_static(&ics_info);

    type_register_static(&icp_info);

}

hw/intc/xics_kvm.c

+33 −30

File changed.

Preview size limit exceeded, changes collapsed.

hw/intc/xics_spapr.c

0 → 100644
+434 −0

File added.

Preview size limit exceeded, changes collapsed.