Commit 1a632032 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging 



X86 queue, 2015-07-07

Patch "target-i386: emulate CPUID level of real hardware" was removed after the
2015-07-03 pull request.

# gpg: Signature made Tue Jul  7 15:46:23 2015 BST using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-pull-request:
  target-i386: avoid overflow in the tsc-frequency property
  i386: Introduce ARAT CPU feature

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 30c6672a 06ef227e

include/hw/i386/pc.h

+6 −1
Original line number Diff line number Diff line
@@ -293,7 +293,12 @@ int e820_get_num_entries(void); 
bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);



#define PC_COMPAT_2_3 \

        HW_COMPAT_2_3

        HW_COMPAT_2_3 \

        {\

            .driver   = TYPE_X86_CPU,\

            .property = "arat",\

            .value    = "off",\

        },



#define PC_COMPAT_2_2 \

        PC_COMPAT_2_3 \

target-i386/cpu.c

+32 −1
Original line number Diff line number Diff line
@@ -286,6 +286,17 @@ static const char *cpuid_xsave_feature_name[] = { 
    NULL, NULL, NULL, NULL,

};



static const char *cpuid_6_feature_name[] = {

    NULL, NULL, "arat", NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};



#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)

#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \

          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
@@ -341,6 +352,7 @@ static const char *cpuid_xsave_feature_name[] = { 
          CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,

          CPUID_7_0_EBX_RDSEED */

#define TCG_APM_FEATURES 0

#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT





typedef struct FeatureWordInfo {
@@ -410,6 +422,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
        .cpuid_reg = R_EAX,

        .tcg_features = 0,

    },

    [FEAT_6_EAX] = {

        .feat_names = cpuid_6_feature_name,

        .cpuid_eax = 6, .cpuid_reg = R_EAX,

        .tcg_features = TCG_6_EAX_FEATURES,

    },

};



typedef struct X86RegisterInfo32 {
@@ -1003,6 +1020,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_LAHF_LM,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",

    },
@@ -1032,6 +1051,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Xeon E312xx (Sandy Bridge)",

    },
@@ -1064,6 +1085,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_EXT3_LAHF_LM,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",

    },
@@ -1098,6 +1121,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Core Processor (Haswell, no TSX)",

    },    {
@@ -1132,6 +1157,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_7_0_EBX_RTM,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Core Processor (Haswell)",

    },
@@ -1168,6 +1195,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_7_0_EBX_SMAP,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Core Processor (Broadwell, no TSX)",

    },
@@ -1204,6 +1233,8 @@ static X86CPUDefinition builtin_x86_defs[] = { 
            CPUID_7_0_EBX_SMAP,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .xlevel = 0x8000000A,

        .model_id = "Intel Core Processor (Broadwell)",

    },
@@ -2359,7 +2390,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 
        break;

    case 6:

        /* Thermal and Power Leaf */

        *eax = 0;

        *eax = env->features[FEAT_6_EAX];

        *ebx = 0;

        *ecx = 0;

        *edx = 0;

target-i386/cpu.h

+4 −1
Original line number Diff line number Diff line
@@ -415,6 +415,7 @@ typedef enum FeatureWord { 
    FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */

    FEAT_SVM,           /* CPUID[8000_000A].EDX */

    FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */

    FEAT_6_EAX,         /* CPUID[6].EAX */

    FEATURE_WORDS,

} FeatureWord;
@@ -580,6 +581,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_XSAVE_XGETBV1    (1U << 2)

#define CPUID_XSAVE_XSAVES     (1U << 3)



#define CPUID_6_EAX_ARAT       (1U << 2)



/* CPUID[0x80000007].EDX flags: */

#define CPUID_APM_INVTSC       (1U << 8)
@@ -959,7 +962,7 @@ typedef struct CPUX86State { 
    uint8_t has_error_code;

    uint32_t sipi_vector;

    bool tsc_valid;

    int tsc_khz;

    int64_t tsc_khz;

    void *kvm_xsave_buf;



    uint64_t mcg_cap;

target-i386/kvm.c

+2 −0
Original line number Diff line number Diff line
@@ -238,6 +238,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, 
        if (!kvm_irqchip_in_kernel()) {

            ret &= ~CPUID_EXT_X2APIC;

        }

    } else if (function == 6 && reg == R_EAX) {

        ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */

    } else if (function == 0x80000001 && reg == R_EDX) {

        /* On Intel, kvm returns cpuid according to the Intel spec,

         * so add missing bits according to the AMD spec: