Loading target-mips/mips-defs.h +3 −3 Original line number Diff line number Diff line Loading @@ -18,9 +18,9 @@ #define TARGET_LONG_BITS 32 #endif /* Strictly follow the architecture standard: Disallow "special" instruction handling for PMON/SPIM, force cycle-dependent Count/Compare maintenance. */ /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ //#define MIPS_STRICT_STANDARD 1 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ Loading
target-mips/mips-defs.h +3 −3 Original line number Diff line number Diff line Loading @@ -18,9 +18,9 @@ #define TARGET_LONG_BITS 32 #endif /* Strictly follow the architecture standard: Disallow "special" instruction handling for PMON/SPIM, force cycle-dependent Count/Compare maintenance. */ /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ //#define MIPS_STRICT_STANDARD 1 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */