tcg/aarch64: Fully convert tcg_target_op_def

#undef REG0

}

static const TCGTargetOpDef aarch64_op_defs[] = {

    { INDEX_op_exit_tb, { } },

    { INDEX_op_goto_tb, { } },

    { INDEX_op_br, { } },

    { INDEX_op_goto_ptr, { "r" } },

    { INDEX_op_ld8u_i32, { "r", "r" } },

    { INDEX_op_ld8s_i32, { "r", "r" } },

    { INDEX_op_ld16u_i32, { "r", "r" } },

    { INDEX_op_ld16s_i32, { "r", "r" } },

    { INDEX_op_ld_i32, { "r", "r" } },

    { INDEX_op_ld8u_i64, { "r", "r" } },

    { INDEX_op_ld8s_i64, { "r", "r" } },

    { INDEX_op_ld16u_i64, { "r", "r" } },

    { INDEX_op_ld16s_i64, { "r", "r" } },

    { INDEX_op_ld32u_i64, { "r", "r" } },

    { INDEX_op_ld32s_i64, { "r", "r" } },

    { INDEX_op_ld_i64, { "r", "r" } },

    { INDEX_op_st8_i32, { "rZ", "r" } },

    { INDEX_op_st16_i32, { "rZ", "r" } },

    { INDEX_op_st_i32, { "rZ", "r" } },

    { INDEX_op_st8_i64, { "rZ", "r" } },

    { INDEX_op_st16_i64, { "rZ", "r" } },

    { INDEX_op_st32_i64, { "rZ", "r" } },

    { INDEX_op_st_i64, { "rZ", "r" } },

    { INDEX_op_add_i32, { "r", "r", "rA" } },

    { INDEX_op_add_i64, { "r", "r", "rA" } },

    { INDEX_op_sub_i32, { "r", "r", "rA" } },

    { INDEX_op_sub_i64, { "r", "r", "rA" } },

    { INDEX_op_mul_i32, { "r", "r", "r" } },

    { INDEX_op_mul_i64, { "r", "r", "r" } },

    { INDEX_op_div_i32, { "r", "r", "r" } },

    { INDEX_op_div_i64, { "r", "r", "r" } },

    { INDEX_op_divu_i32, { "r", "r", "r" } },

    { INDEX_op_divu_i64, { "r", "r", "r" } },

    { INDEX_op_rem_i32, { "r", "r", "r" } },

    { INDEX_op_rem_i64, { "r", "r", "r" } },

    { INDEX_op_remu_i32, { "r", "r", "r" } },

    { INDEX_op_remu_i64, { "r", "r", "r" } },

    { INDEX_op_and_i32, { "r", "r", "rL" } },

    { INDEX_op_and_i64, { "r", "r", "rL" } },

    { INDEX_op_or_i32, { "r", "r", "rL" } },

    { INDEX_op_or_i64, { "r", "r", "rL" } },

    { INDEX_op_xor_i32, { "r", "r", "rL" } },

    { INDEX_op_xor_i64, { "r", "r", "rL" } },

    { INDEX_op_andc_i32, { "r", "r", "rL" } },

    { INDEX_op_andc_i64, { "r", "r", "rL" } },

    { INDEX_op_orc_i32, { "r", "r", "rL" } },

    { INDEX_op_orc_i64, { "r", "r", "rL" } },

    { INDEX_op_eqv_i32, { "r", "r", "rL" } },

    { INDEX_op_eqv_i64, { "r", "r", "rL" } },

    { INDEX_op_neg_i32, { "r", "r" } },

    { INDEX_op_neg_i64, { "r", "r" } },

    { INDEX_op_not_i32, { "r", "r" } },

    { INDEX_op_not_i64, { "r", "r" } },

    { INDEX_op_shl_i32, { "r", "r", "ri" } },

    { INDEX_op_shr_i32, { "r", "r", "ri" } },

    { INDEX_op_sar_i32, { "r", "r", "ri" } },

    { INDEX_op_rotl_i32, { "r", "r", "ri" } },

    { INDEX_op_rotr_i32, { "r", "r", "ri" } },

    { INDEX_op_clz_i32, { "r", "r", "rAL" } },

    { INDEX_op_ctz_i32, { "r", "r", "rAL" } },

    { INDEX_op_shl_i64, { "r", "r", "ri" } },

    { INDEX_op_shr_i64, { "r", "r", "ri" } },

    { INDEX_op_sar_i64, { "r", "r", "ri" } },

    { INDEX_op_rotl_i64, { "r", "r", "ri" } },

    { INDEX_op_rotr_i64, { "r", "r", "ri" } },

    { INDEX_op_clz_i64, { "r", "r", "rAL" } },

    { INDEX_op_ctz_i64, { "r", "r", "rAL" } },

    { INDEX_op_brcond_i32, { "r", "rA" } },

    { INDEX_op_brcond_i64, { "r", "rA" } },

    { INDEX_op_setcond_i32, { "r", "r", "rA" } },

    { INDEX_op_setcond_i64, { "r", "r", "rA" } },

    { INDEX_op_movcond_i32, { "r", "r", "rA", "rZ", "rZ" } },

    { INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } },

    { INDEX_op_qemu_ld_i32, { "r", "l" } },

    { INDEX_op_qemu_ld_i64, { "r", "l" } },

    { INDEX_op_qemu_st_i32, { "lZ", "l" } },

    { INDEX_op_qemu_st_i64, { "lZ", "l" } },

    { INDEX_op_bswap16_i32, { "r", "r" } },

    { INDEX_op_bswap32_i32, { "r", "r" } },

    { INDEX_op_bswap16_i64, { "r", "r" } },

    { INDEX_op_bswap32_i64, { "r", "r" } },

    { INDEX_op_bswap64_i64, { "r", "r" } },

    { INDEX_op_ext8s_i32, { "r", "r" } },

    { INDEX_op_ext16s_i32, { "r", "r" } },

    { INDEX_op_ext8u_i32, { "r", "r" } },

    { INDEX_op_ext16u_i32, { "r", "r" } },

    { INDEX_op_ext8s_i64, { "r", "r" } },

    { INDEX_op_ext16s_i64, { "r", "r" } },

    { INDEX_op_ext32s_i64, { "r", "r" } },

    { INDEX_op_ext8u_i64, { "r", "r" } },

    { INDEX_op_ext16u_i64, { "r", "r" } },

    { INDEX_op_ext32u_i64, { "r", "r" } },

    { INDEX_op_ext_i32_i64, { "r", "r" } },

    { INDEX_op_extu_i32_i64, { "r", "r" } },

    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },

    { INDEX_op_deposit_i64, { "r", "0", "rZ" } },

    { INDEX_op_extract_i32, { "r", "r" } },

    { INDEX_op_extract_i64, { "r", "r" } },

    { INDEX_op_sextract_i32, { "r", "r" } },

    { INDEX_op_sextract_i64, { "r", "r" } },

    { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },

    { INDEX_op_muluh_i64, { "r", "r", "r" } },

    { INDEX_op_mulsh_i64, { "r", "r", "r" } },

    { INDEX_op_mb, { } },

    { -1 },

};

static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)

{

    int i, n = ARRAY_SIZE(aarch64_op_defs);

    static const TCGTargetOpDef r = { .args_ct_str = { "r" } };

    static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };

    static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };

    static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };

    static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };

    static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };

    static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };

    static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };

    static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };

    static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };

    static const TCGTargetOpDef r_r_rAL

        = { .args_ct_str = { "r", "r", "rAL" } };

    static const TCGTargetOpDef dep

        = { .args_ct_str = { "r", "0", "rZ" } };

    static const TCGTargetOpDef movc

        = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };

    static const TCGTargetOpDef add2

        = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };

    switch (op) {

    case INDEX_op_goto_ptr:

        return &r;

    for (i = 0; i < n; ++i) {

        if (aarch64_op_defs[i].op == op) {

            return &aarch64_op_defs[i];

        }

    }

    case INDEX_op_ld8u_i32:

    case INDEX_op_ld8s_i32:

    case INDEX_op_ld16u_i32:

    case INDEX_op_ld16s_i32:

    case INDEX_op_ld_i32:

    case INDEX_op_ld8u_i64:

    case INDEX_op_ld8s_i64:

    case INDEX_op_ld16u_i64:

    case INDEX_op_ld16s_i64:

    case INDEX_op_ld32u_i64:

    case INDEX_op_ld32s_i64:

    case INDEX_op_ld_i64:

    case INDEX_op_neg_i32:

    case INDEX_op_neg_i64:

    case INDEX_op_not_i32:

    case INDEX_op_not_i64:

    case INDEX_op_bswap16_i32:

    case INDEX_op_bswap32_i32:

    case INDEX_op_bswap16_i64:

    case INDEX_op_bswap32_i64:

    case INDEX_op_bswap64_i64:

    case INDEX_op_ext8s_i32:

    case INDEX_op_ext16s_i32:

    case INDEX_op_ext8u_i32:

    case INDEX_op_ext16u_i32:

    case INDEX_op_ext8s_i64:

    case INDEX_op_ext16s_i64:

    case INDEX_op_ext32s_i64:

    case INDEX_op_ext8u_i64:

    case INDEX_op_ext16u_i64:

    case INDEX_op_ext32u_i64:

    case INDEX_op_ext_i32_i64:

    case INDEX_op_extu_i32_i64:

    case INDEX_op_extract_i32:

    case INDEX_op_extract_i64:

    case INDEX_op_sextract_i32:

    case INDEX_op_sextract_i64:

        return &r_r;

    case INDEX_op_st8_i32:

    case INDEX_op_st16_i32:

    case INDEX_op_st_i32:

    case INDEX_op_st8_i64:

    case INDEX_op_st16_i64:

    case INDEX_op_st32_i64:

    case INDEX_op_st_i64:

        return &rZ_r;

    case INDEX_op_add_i32:

    case INDEX_op_add_i64:

    case INDEX_op_sub_i32:

    case INDEX_op_sub_i64:

    case INDEX_op_setcond_i32:

    case INDEX_op_setcond_i64:

        return &r_r_rA;

    case INDEX_op_mul_i32:

    case INDEX_op_mul_i64:

    case INDEX_op_div_i32:

    case INDEX_op_div_i64:

    case INDEX_op_divu_i32:

    case INDEX_op_divu_i64:

    case INDEX_op_rem_i32:

    case INDEX_op_rem_i64:

    case INDEX_op_remu_i32:

    case INDEX_op_remu_i64:

    case INDEX_op_muluh_i64:

    case INDEX_op_mulsh_i64:

        return &r_r_r;

    case INDEX_op_and_i32:

    case INDEX_op_and_i64:

    case INDEX_op_or_i32:

    case INDEX_op_or_i64:

    case INDEX_op_xor_i32:

    case INDEX_op_xor_i64:

    case INDEX_op_andc_i32:

    case INDEX_op_andc_i64:

    case INDEX_op_orc_i32:

    case INDEX_op_orc_i64:

    case INDEX_op_eqv_i32:

    case INDEX_op_eqv_i64:

        return &r_r_rL;

    case INDEX_op_shl_i32:

    case INDEX_op_shr_i32:

    case INDEX_op_sar_i32:

    case INDEX_op_rotl_i32:

    case INDEX_op_rotr_i32:

    case INDEX_op_shl_i64:

    case INDEX_op_shr_i64:

    case INDEX_op_sar_i64:

    case INDEX_op_rotl_i64:

    case INDEX_op_rotr_i64:

        return &r_r_ri;

    case INDEX_op_clz_i32:

    case INDEX_op_ctz_i32:

    case INDEX_op_clz_i64:

    case INDEX_op_ctz_i64:

        return &r_r_rAL;

    case INDEX_op_brcond_i32:

    case INDEX_op_brcond_i64:

        return &r_rA;

    case INDEX_op_movcond_i32:

    case INDEX_op_movcond_i64:

        return &movc;

    case INDEX_op_qemu_ld_i32:

    case INDEX_op_qemu_ld_i64:

        return &r_l;

    case INDEX_op_qemu_st_i32:

    case INDEX_op_qemu_st_i64:

        return &lZ_l;

    case INDEX_op_deposit_i32:

    case INDEX_op_deposit_i64:

        return &dep;

    case INDEX_op_add2_i32:

    case INDEX_op_add2_i64:

    case INDEX_op_sub2_i32:

    case INDEX_op_sub2_i64:

        return &add2;

    default:

        return NULL;

    }

}

static void tcg_target_init(TCGContext *s)

{