Commit 18896679 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-2018-06-27' into staging 



MIPS queue

# gpg: Signature made Wed 27 Jun 2018 19:16:23 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-2018-06-27:
  target/mips: Fix gdbstub to read/write 64 bit FP registers
  target/mips: Fix data type for offset
  target/mips: Update gen_flt_ldst()
  target/mips: Fix microMIPS on reset
  target/mips: Raise a RI when given fs is n/a from CTC1
  hw/pci-host/xilinx-pcie: don't make "io" region be RAM
  hw/mips/mips_malta: don't make bios region 'nomigrate'
  hw/mips/boston: don't make flash region 'nomigrate'
  MAINTAINERS: update target-mips maintainers

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 1571a23c 8e0b373f

MAINTAINERS

+3 −3
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ F: disas/microblaze.c 


MIPS

M: Aurelien Jarno <aurelien@aurel32.net>

M: Yongbok Kim <yongbok.kim@mips.com>

M: Aleksandar Markovic <aleksandar.markovic@mips.com>

S: Maintained

F: target/mips/

F: hw/mips/
@@ -718,7 +718,7 @@ S: Maintained 
F: hw/mips/mips_malta.c



Mipssim

M: Yongbok Kim <yongbok.kim@mips.com>

M: Aleksandar Markovic <aleksandar.markovic@mips.com>

S: Odd Fixes

F: hw/mips/mips_mipssim.c

F: hw/net/mipsnet.c
@@ -729,7 +729,7 @@ S: Maintained 
F: hw/mips/mips_r4k.c



Fulong 2E

M: Yongbok Kim <yongbok.kim@mips.com>

M: Aleksandar Markovic <aleksandar.markovic@mips.com>

S: Odd Fixes

F: hw/mips/mips_fulong2e.c

F: hw/isa/vt82c686.c

hw/mips/boston.c

+1 −2
Original line number Diff line number Diff line
@@ -471,8 +471,7 @@ static void boston_mach_init(MachineState *machine) 
    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);



    flash =  g_new(MemoryRegion, 1);

    memory_region_init_rom_nomigrate(flash, NULL,

                                     "boston.flash", 128 * M_BYTE, &err);

    memory_region_init_rom(flash, NULL, "boston.flash", 128 * M_BYTE, &err);

    memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);



    ddr = g_new(MemoryRegion, 1);

hw/mips/mips_malta.c

+1 −1
Original line number Diff line number Diff line
@@ -1152,7 +1152,7 @@ void mips_malta_init(MachineState *machine) 
     * handled by an overlapping region as the resulting ROM code subpage

     * regions are not executable.

     */

    memory_region_init_ram_nomigrate(bios_copy, NULL, "bios.1fc", BIOS_SIZE,

    memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,

                           &error_fatal);

    if (!rom_copy(memory_region_get_ram_ptr(bios_copy),

                  FLASH_ADDRESS, BIOS_SIZE)) {

hw/pci-host/xilinx-pcie.c

+2 −3
Original line number Diff line number Diff line
@@ -120,9 +120,8 @@ static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) 
    memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);

    memory_region_set_enabled(&s->mmio, false);



    /* dummy I/O region */

    memory_region_init_ram_nomigrate(&s->io, OBJECT(s), "io", 16, NULL);

    memory_region_set_enabled(&s->io, false);

    /* dummy PCI I/O region (not visible to the CPU) */

    memory_region_init(&s->io, OBJECT(s), "io", 16);



    /* interrupt out */

    qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);

target/mips/gdbstub.c

+2 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 
            return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0);

        default:

            if (env->CP0_Status & (1 << CP0St_FR)) {

                return gdb_get_regl(mem_buf,

                return gdb_get_reg64(mem_buf,

                    env->active_fpu.fpr[n - 38].d);

            } else {

                return gdb_get_regl(mem_buf,
@@ -100,6 +100,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 
            break;

        default:

            if (env->CP0_Status & (1 << CP0St_FR)) {

                uint64_t tmp = ldq_p(mem_buf);

                env->active_fpu.fpr[n - 38].d = tmp;

            } else {

                env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;