Commit 17ebc8c1 authored by Bastian Koppelmann's avatar Bastian Koppelmann
Browse files

target/tricore: Implement a qemu excptions helper 



this helper is only used to raise qemu specific exceptions. We use this
helper to raise it on breakpoints.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarBastian Koppelmann <kbastian@mail.uni-paderborn.de>
parent 1fae1851

target/tricore/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -153,3 +153,4 @@ DEF_HELPER_2(psw_write, void, env, i32) 
DEF_HELPER_1(psw_read, i32, env)

/* Exceptions */

DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)

DEF_HELPER_2(qemu_excp, noreturn, env, i32)

target/tricore/op_helper.c

+7 −0
Original line number Diff line number Diff line
@@ -107,6 +107,13 @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class, 
    raise_exception_sync_internal(env, class, tin, pc, 0);

}



void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)

{

    CPUState *cs = env_cpu(env);

    cs->exception_index = excp;

    cpu_loop_exit(cs);

}



/* Addressing mode helper */



static uint16_t reverse16(uint16_t val)

target/tricore/translate.c

+19 −1
Original line number Diff line number Diff line
@@ -3261,6 +3261,15 @@ static void generate_trap(DisasContext *ctx, int class, int tin) 
    tcg_temp_free(tintemp);

}



static void generate_qemu_excp(DisasContext *ctx, int excp)

{

    TCGv_i32 tmp = tcg_const_i32(excp);

    gen_save_pc(ctx->base.pc_next);

    gen_helper_qemu_excp(cpu_env, tmp);

    ctx->base.is_jmp = DISAS_NORETURN;

    tcg_temp_free(tmp);

}



static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,

                                   TCGv r2, int16_t address)

{
@@ -8808,7 +8817,16 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 
static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,

                                      const CPUBreakpoint *bp)

{

    return false;

    DisasContext *ctx = container_of(dcbase, DisasContext, base);

    generate_qemu_excp(ctx, EXCP_DEBUG);

    /*

     * The address covered by the breakpoint must be included in

     * [tb->pc, tb->pc + tb->size) in order to for it to be

     * properly cleared -- thus we increment the PC here so that

     * the logic setting tb->size below does the right thing.

     */

    ctx->base.pc_next += 4;

    return true;

}



static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)