Commit 174d4d21 authored by Aurelien Jarno's avatar Aurelien Jarno
Browse files

tcg/mips: Implement muls2_i32 



Reviewed-by: default avatarRichard Henderson <rth@twiddle.net>
Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent c334a388

tcg/mips/tcg-target.c

+6 −0
Original line number Diff line number Diff line
@@ -1413,6 +1413,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 
        tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);

#endif

        break;

    case INDEX_op_muls2_i32:

        tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]);

        tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);

        tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0);

        break;

    case INDEX_op_mulu2_i32:

        tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]);

        tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0);
@@ -1595,6 +1600,7 @@ static const TCGTargetOpDef mips_op_defs[] = { 


    { INDEX_op_add_i32, { "r", "rZ", "rJ" } },

    { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },

    { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },

    { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },

    { INDEX_op_div_i32, { "r", "rZ", "rZ" } },

    { INDEX_op_divu_i32, { "r", "rZ", "rZ" } },

tcg/mips/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ typedef enum { 
#define TCG_TARGET_HAS_orc_i32          0

#define TCG_TARGET_HAS_eqv_i32          0

#define TCG_TARGET_HAS_nand_i32         0

#define TCG_TARGET_HAS_muls2_i32        0

#define TCG_TARGET_HAS_muls2_i32        1



/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */

#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \