Commit 1743d55c authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: A64: Fix shifts into sign bit 



Fix attempts to shift into the sign bit of an int, which is undefined
behaviour in C and warned about by the clang sanitizer.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Message-id: 1423233250-15853-2-git-send-email-peter.maydell@linaro.org
parent 56073970

target-arm/translate-a64.c

+3 −3
Original line number Diff line number Diff line
@@ -1077,7 +1077,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) 
{

    uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;



    if (insn & (1 << 31)) {

    if (insn & (1U << 31)) {

        /* C5.6.26 BL Branch with link */

        tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);

    }
@@ -1271,7 +1271,7 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) 
    TCGv_i32 nzcv = tcg_temp_new_i32();



    /* build bit 31, N */

    tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31));

    tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31));

    /* build bit 30, Z */

    tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);

    tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
@@ -1296,7 +1296,7 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt) 
    tcg_gen_trunc_i64_i32(nzcv, tcg_rt);



    /* bit 31, N */

    tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31));

    tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31));

    /* bit 30, Z */

    tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));

    tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);