Commit 1695cd61 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Decode aa64 armv8.3 fcadd 



Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180228193125.20577-12-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 0438f037

target/arm/helper.h

+7 −0
Original line number Diff line number Diff line
@@ -578,6 +578,13 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, 
DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,

                   void, ptr, ptr, ptr, ptr, i32)



#ifdef TARGET_AARCH64

#include "helper-a64.h"

#endif

target/arm/translate-a64.c

+47 −1
Original line number Diff line number Diff line
@@ -713,6 +713,21 @@ static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd, 
                       is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);

}



/* Expand a 3-operand + fpstatus pointer + simd data value operation using

 * an out-of-line helper.

 */

static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,

                              int rm, bool is_fp16, int data,

                              gen_helper_gvec_3_ptr *fn)

{

    TCGv_ptr fpst = get_fpstatus_ptr(is_fp16);

    tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),

                       vec_full_reg_offset(s, rn),

                       vec_full_reg_offset(s, rm), fpst,

                       is_q ? 16 : 8, vec_full_reg_size(s), data, fn);

    tcg_temp_free_ptr(fpst);

}



/* Set ZF and NF based on a 64 bit result. This is alas fiddlier

 * than the 32 bit equivalent.

 */
@@ -10816,7 +10831,7 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) 
    int size = extract32(insn, 22, 2);

    bool u = extract32(insn, 29, 1);

    bool is_q = extract32(insn, 30, 1);

    int feature;

    int feature, rot;



    switch (u * 16 + opcode) {

    case 0x10: /* SQRDMLAH (vector) */
@@ -10827,6 +10842,16 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) 
        }

        feature = ARM_FEATURE_V8_RDM;

        break;

    case 0xc: /* FCADD, #90 */

    case 0xe: /* FCADD, #270 */

        if (size == 0

            || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))

            || (size == 3 && !is_q)) {

            unallocated_encoding(s);

            return;

        }

        feature = ARM_FEATURE_V8_FCMA;

        break;

    default:

        unallocated_encoding(s);

        return;
@@ -10866,6 +10891,27 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) 
        }

        return;



    case 0xc: /* FCADD, #90 */

    case 0xe: /* FCADD, #270 */

        rot = extract32(opcode, 1, 1);

        switch (size) {

        case 1:

            gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,

                              gen_helper_gvec_fcaddh);

            break;

        case 2:

            gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,

                              gen_helper_gvec_fcadds);

            break;

        case 3:

            gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,

                              gen_helper_gvec_fcaddd);

            break;

        default:

            g_assert_not_reached();

        }

        return;



    default:

        g_assert_not_reached();

    }

target/arm/vec_helper.c

+97 −0
Original line number Diff line number Diff line
@@ -22,8 +22,21 @@ 
#include "exec/exec-all.h"

#include "exec/helper-proto.h"

#include "tcg/tcg-gvec-desc.h"

#include "fpu/softfloat.h"





/* Note that vector data is stored in host-endian 64-bit chunks,

   so addressing units smaller than that needs a host-endian fixup.  */

#ifdef HOST_WORDS_BIGENDIAN

#define H1(x)  ((x) ^ 7)

#define H2(x)  ((x) ^ 3)

#define H4(x)  ((x) ^ 1)

#else

#define H1(x)  (x)

#define H2(x)  (x)

#define H4(x)  (x)

#endif



#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q



static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
@@ -181,3 +194,87 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm, 
    }

    clear_tail(d, opr_sz, simd_maxsz(desc));

}



void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,

                         void *vfpst, uint32_t desc)

{

    uintptr_t opr_sz = simd_oprsz(desc);

    float16 *d = vd;

    float16 *n = vn;

    float16 *m = vm;

    float_status *fpst = vfpst;

    uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);

    uint32_t neg_imag = neg_real ^ 1;

    uintptr_t i;



    /* Shift boolean to the sign bit so we can xor to negate.  */

    neg_real <<= 15;

    neg_imag <<= 15;



    for (i = 0; i < opr_sz / 2; i += 2) {

        float16 e0 = n[H2(i)];

        float16 e1 = m[H2(i + 1)] ^ neg_imag;

        float16 e2 = n[H2(i + 1)];

        float16 e3 = m[H2(i)] ^ neg_real;



        d[H2(i)] = float16_add(e0, e1, fpst);

        d[H2(i + 1)] = float16_add(e2, e3, fpst);

    }

    clear_tail(d, opr_sz, simd_maxsz(desc));

}



void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,

                         void *vfpst, uint32_t desc)

{

    uintptr_t opr_sz = simd_oprsz(desc);

    float32 *d = vd;

    float32 *n = vn;

    float32 *m = vm;

    float_status *fpst = vfpst;

    uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);

    uint32_t neg_imag = neg_real ^ 1;

    uintptr_t i;



    /* Shift boolean to the sign bit so we can xor to negate.  */

    neg_real <<= 31;

    neg_imag <<= 31;



    for (i = 0; i < opr_sz / 4; i += 2) {

        float32 e0 = n[H4(i)];

        float32 e1 = m[H4(i + 1)] ^ neg_imag;

        float32 e2 = n[H4(i + 1)];

        float32 e3 = m[H4(i)] ^ neg_real;



        d[H4(i)] = float32_add(e0, e1, fpst);

        d[H4(i + 1)] = float32_add(e2, e3, fpst);

    }

    clear_tail(d, opr_sz, simd_maxsz(desc));

}



void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,

                         void *vfpst, uint32_t desc)

{

    uintptr_t opr_sz = simd_oprsz(desc);

    float64 *d = vd;

    float64 *n = vn;

    float64 *m = vm;

    float_status *fpst = vfpst;

    uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);

    uint64_t neg_imag = neg_real ^ 1;

    uintptr_t i;



    /* Shift boolean to the sign bit so we can xor to negate.  */

    neg_real <<= 63;

    neg_imag <<= 63;



    for (i = 0; i < opr_sz / 8; i += 2) {

        float64 e0 = n[i];

        float64 e1 = m[i + 1] ^ neg_imag;

        float64 e2 = n[i + 1];

        float64 e3 = m[i] ^ neg_real;



        d[i] = float64_add(e0, e1, fpst);

        d[i + 1] = float64_add(e2, e3, fpst);

    }

    clear_tail(d, opr_sz, simd_maxsz(desc));

}