Commit 1680d485 authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Merge remote-tracking branch 'rth/tcg-ldst-6' into staging 



# By Richard Henderson
# Via Richard Henderson
* rth/tcg-ldst-6:
  target-alpha: Convert to new ldst opcodes
  tcg-ppc64: Support new ldst opcodes
  tcg-ppc: Support new ldst opcodes
  tcg-ppc64: Convert to le/be ldst helpers
  tcg-ppc: Convert to le/be ldst helpers
  tcg-ppc64: Use TCGMemOp within qemu_ldst routines
  tcg-ppc: Use TCGMemOp within qemu_ldst routines
  tcg-arm: Improve GUEST_BASE qemu_ld/st
  tcg-arm: Convert to new ldst opcodes
  tcg-arm: Tidy variable naming convention in qemu_ld/st
  tcg-arm: Convert to le/be ldst helpers
  tcg-arm: Use TCGMemOp within qemu_ldst routines
  tcg-i386: Support new ldst opcodes
  tcg-i386: Remove "cb" output restriction from qemu_st8 for i386
  tcg-i386: Tidy softmmu routines
  tcg-i386: Use TCGMemOp within qemu_ldst routines
  tcg: Use TCGMemOp for TCGLabelQemuLdst.opc

Message-id: 1381620683-4568-1-git-send-email-rth@twiddle.net
Signed-off-by: default avatarAnthony Liguori <aliguori@amazon.com>
parents ded77da3 f8da40ae

target-alpha/translate.c

+15 −34
Original line number Diff line number Diff line
@@ -168,44 +168,38 @@ static inline ExitStatus gen_invalid(DisasContext *ctx) 


static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    tcg_gen_qemu_ld32u(tmp, t1, flags);

    tcg_gen_trunc_i64_i32(tmp32, tmp);

    tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);

    gen_helper_memory_to_f(t0, tmp32);

    tcg_temp_free_i32(tmp32);

    tcg_temp_free(tmp);

}



static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    tcg_gen_qemu_ld64(tmp, t1, flags);

    tcg_gen_qemu_ld_i64(tmp, t1, flags, MO_LEQ);

    gen_helper_memory_to_g(t0, tmp);

    tcg_temp_free(tmp);

}



static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)

{

    TCGv tmp = tcg_temp_new();

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    tcg_gen_qemu_ld32u(tmp, t1, flags);

    tcg_gen_trunc_i64_i32(tmp32, tmp);

    tcg_gen_qemu_ld_i32(tmp32, t1, flags, MO_LEUL);

    gen_helper_memory_to_s(t0, tmp32);

    tcg_temp_free_i32(tmp32);

    tcg_temp_free(tmp);

}



static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)

{

    tcg_gen_qemu_ld32s(t0, t1, flags);

    tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);

    tcg_gen_mov_i64(cpu_lock_addr, t1);

    tcg_gen_mov_i64(cpu_lock_value, t0);

}



static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)

{

    tcg_gen_qemu_ld64(t0, t1, flags);

    tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);

    tcg_gen_mov_i64(cpu_lock_addr, t1);

    tcg_gen_mov_i64(cpu_lock_value, t0);

}
@@ -247,11 +241,8 @@ static inline void gen_load_mem(DisasContext *ctx, 
static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)

{

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    TCGv tmp = tcg_temp_new();

    gen_helper_f_to_memory(tmp32, t0);

    tcg_gen_extu_i32_i64(tmp, tmp32);

    tcg_gen_qemu_st32(tmp, t1, flags);

    tcg_temp_free(tmp);

    tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);

    tcg_temp_free_i32(tmp32);

}
@@ -259,18 +250,15 @@ static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags) 
{

    TCGv tmp = tcg_temp_new();

    gen_helper_g_to_memory(tmp, t0);

    tcg_gen_qemu_st64(tmp, t1, flags);

    tcg_gen_qemu_st_i64(tmp, t1, flags, MO_LEQ);

    tcg_temp_free(tmp);

}



static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)

{

    TCGv_i32 tmp32 = tcg_temp_new_i32();

    TCGv tmp = tcg_temp_new();

    gen_helper_s_to_memory(tmp32, t0);

    tcg_gen_extu_i32_i64(tmp, tmp32);

    tcg_gen_qemu_st32(tmp, t1, flags);

    tcg_temp_free(tmp);

    tcg_gen_qemu_st_i32(tmp32, t1, flags, MO_LEUL);

    tcg_temp_free_i32(tmp32);

}
@@ -348,18 +336,11 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, 
        tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail);



        val = tcg_temp_new();

        if (quad) {

            tcg_gen_qemu_ld64(val, addr, ctx->mem_idx);

        } else {

            tcg_gen_qemu_ld32s(val, addr, ctx->mem_idx);

        }

        tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, quad ? MO_LEQ : MO_LESL);

        tcg_gen_brcond_i64(TCG_COND_NE, val, cpu_lock_value, lab_fail);



        if (quad) {

            tcg_gen_qemu_st64(cpu_ir[ra], addr, ctx->mem_idx);

        } else {

            tcg_gen_qemu_st32(cpu_ir[ra], addr, ctx->mem_idx);

        }

        tcg_gen_qemu_st_i64(cpu_ir[ra], addr, ctx->mem_idx,

                            quad ? MO_LEQ : MO_LEUL);

        tcg_gen_movi_i64(cpu_ir[ra], 1);

        tcg_gen_br(lab_done);
@@ -2966,11 +2947,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) 
                goto invalid_opc;

            case 0xA:

                /* Longword virtual access with protection check (hw_ldl/w) */

                tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX);

                tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_KERNEL_IDX, MO_LESL);

                break;

            case 0xB:

                /* Quadword virtual access with protection check (hw_ldq/w) */

                tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX);

                tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_KERNEL_IDX, MO_LEQ);

                break;

            case 0xC:

                /* Longword virtual access with alt access mode (hw_ldl/a)*/
@@ -2981,12 +2962,12 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) 
            case 0xE:

                /* Longword virtual access with alternate access mode and

                   protection checks (hw_ldl/wa) */

                tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_USER_IDX);

                tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_USER_IDX, MO_LESL);

                break;

            case 0xF:

                /* Quadword virtual access with alternate access mode and

                   protection checks (hw_ldq/wa) */

                tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_USER_IDX);

                tcg_gen_qemu_ld_i64(cpu_ir[ra], addr, MMU_USER_IDX, MO_LEQ);

                break;

            }

            tcg_temp_free(addr);

tcg/arm/tcg-target.c

+270 −286

File changed.

Preview size limit exceeded, changes collapsed.

tcg/arm/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ extern bool use_idiv_instructions; 
#define TCG_TARGET_HAS_div_i32          use_idiv_instructions

#define TCG_TARGET_HAS_rem_i32          0



#define TCG_TARGET_HAS_new_ldst         0

#define TCG_TARGET_HAS_new_ldst         1



extern bool tcg_target_deposit_valid(int ofs, int len);

#define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid

tcg/i386/tcg-target.c

+282 −361

File changed.

Preview size limit exceeded, changes collapsed.

tcg/i386/tcg-target.h

+1 −1
Original line number Diff line number Diff line
@@ -130,7 +130,7 @@ typedef enum { 
#define TCG_TARGET_HAS_mulsh_i64        0

#endif



#define TCG_TARGET_HAS_new_ldst         0

#define TCG_TARGET_HAS_new_ldst         1



#define TCG_TARGET_deposit_i32_valid(ofs, len) \

    (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \