tcg-arm: Convert to new ldst opcodes (15ecf6e3) · Commits · SUMMER2020 / students / proj-2021291

tcg/arm/tcg-target.c

+37 −70

Original line number	Diff line number	Diff line
		@@ -1367,24 +1367,27 @@ static void tcg_out_qemu_st_slow_path(TCGContext s, TCGLabelQemuLdst lb)
		}
		#endif /* SOFTMMU */

		static void tcg_out_qemu_ld(TCGContext s, const TCGArg args, TCGMemOp opc)
		static void tcg_out_qemu_ld(TCGContext s, const TCGArg args, bool is64)
		{
		TCGReg addrlo, datalo, datahi;
		TCGMemOp bswap = opc & MO_BSWAP;
		TCGMemOp s_bits = opc & MO_SIZE;
		TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
		TCGMemOp opc, bswap;
		#ifdef CONFIG_SOFTMMU
		TCGMemOp s_bits;
		int mem_index;
		TCGReg addrhi, addend;
		TCGReg addend;
		uint8_t *label_ptr;
		#endif

		datalo = *args++;
		datahi = (s_bits == MO_64 ? *args++ : 0);
		datahi = (is64 ? *args++ : 0);
		addrlo = *args++;
		#ifdef CONFIG_SOFTMMU
		addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
		mem_index = *args;
		opc = *args++;
		bswap = opc & MO_BSWAP;

		#ifdef CONFIG_SOFTMMU
		s_bits = opc & MO_SIZE;
		mem_index = *args;
		addend = tcg_out_tlb_read(s, addrlo, addrhi, s_bits, mem_index, 1);

		/* This a conditional BL only to load a pointer within this opcode into LR
		@@ -1514,29 +1517,26 @@ static void tcg_out_qemu_ld(TCGContext s, const TCGArg args, TCGMemOp opc)
		#endif
		}

		static void tcg_out_qemu_st(TCGContext s, const TCGArg args, TCGMemOp opc)
		static void tcg_out_qemu_st(TCGContext s, const TCGArg args, bool is64)
		{
		TCGReg addrlo, datalo, datahi;
		TCGMemOp bswap = opc & MO_BSWAP;
		TCGMemOp s_bits = opc & MO_SIZE;
		TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
		TCGMemOp opc, bswap, s_bits;
		#ifdef CONFIG_SOFTMMU
		int mem_index;
		TCGReg addrhi, addend;
		TCGReg addend;
		uint8_t *label_ptr;
		#endif
		#ifdef TARGET_WORDS_BIGENDIAN
		bswap = 1;
		#else
		bswap = 0;
		#endif

		datalo = *args++;
		datahi = (s_bits == MO_64 ? *args++ : 0);
		datahi = (is64 ? *args++ : 0);
		addrlo = *args++;
		#ifdef CONFIG_SOFTMMU
		addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
		mem_index = *args;
		opc = *args++;
		bswap = opc & MO_BSWAP;
		s_bits = opc & MO_SIZE;

		#ifdef CONFIG_SOFTMMU
		mem_index = *args;
		addend = tcg_out_tlb_read(s, addrlo, addrhi, s_bits, mem_index, 0);

		switch (s_bits) {
		@@ -1902,36 +1902,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
		ARITH_MOV, args[0], 0, 0);
		break;

		case INDEX_op_qemu_ld8u:
		tcg_out_qemu_ld(s, args, MO_UB);
		break;
		case INDEX_op_qemu_ld8s:
		tcg_out_qemu_ld(s, args, MO_SB);
		break;
		case INDEX_op_qemu_ld16u:
		tcg_out_qemu_ld(s, args, MO_TEUW);
		break;
		case INDEX_op_qemu_ld16s:
		tcg_out_qemu_ld(s, args, MO_TESW);
		break;
		case INDEX_op_qemu_ld32:
		tcg_out_qemu_ld(s, args, MO_TEUL);
		break;
		case INDEX_op_qemu_ld64:
		tcg_out_qemu_ld(s, args, MO_TEQ);
		break;

		case INDEX_op_qemu_st8:
		tcg_out_qemu_st(s, args, MO_UB);
		case INDEX_op_qemu_ld_i32:
		tcg_out_qemu_ld(s, args, 0);
		break;
		case INDEX_op_qemu_st16:
		tcg_out_qemu_st(s, args, MO_TEUW);
		case INDEX_op_qemu_ld_i64:
		tcg_out_qemu_ld(s, args, 1);
		break;
		case INDEX_op_qemu_st32:
		tcg_out_qemu_st(s, args, MO_TEUL);
		case INDEX_op_qemu_st_i32:
		tcg_out_qemu_st(s, args, 0);
		break;
		case INDEX_op_qemu_st64:
		tcg_out_qemu_st(s, args, MO_TEQ);
		case INDEX_op_qemu_st_i64:
		tcg_out_qemu_st(s, args, 1);
		break;

		case INDEX_op_bswap16_i32:
		@@ -2015,29 +1996,15 @@ static const TCGTargetOpDef arm_op_defs[] = {
		{ INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } },

		#if TARGET_LONG_BITS == 32
		{ INDEX_op_qemu_ld8u, { "r", "l" } },
		{ INDEX_op_qemu_ld8s, { "r", "l" } },
		{ INDEX_op_qemu_ld16u, { "r", "l" } },
		{ INDEX_op_qemu_ld16s, { "r", "l" } },
		{ INDEX_op_qemu_ld32, { "r", "l" } },
		{ INDEX_op_qemu_ld64, { "r", "r", "l" } },

		{ INDEX_op_qemu_st8, { "s", "s" } },
		{ INDEX_op_qemu_st16, { "s", "s" } },
		{ INDEX_op_qemu_st32, { "s", "s" } },
		{ INDEX_op_qemu_st64, { "s", "s", "s" } },
		{ INDEX_op_qemu_ld_i32, { "r", "l" } },
		{ INDEX_op_qemu_ld_i64, { "r", "r", "l" } },
		{ INDEX_op_qemu_st_i32, { "s", "s" } },
		{ INDEX_op_qemu_st_i64, { "s", "s", "s" } },
		#else
		{ INDEX_op_qemu_ld8u, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld8s, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld16u, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld16s, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld32, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld64, { "r", "r", "l", "l" } },

		{ INDEX_op_qemu_st8, { "s", "s", "s" } },
		{ INDEX_op_qemu_st16, { "s", "s", "s" } },
		{ INDEX_op_qemu_st32, { "s", "s", "s" } },
		{ INDEX_op_qemu_st64, { "s", "s", "s", "s" } },
		{ INDEX_op_qemu_ld_i32, { "r", "l", "l" } },
		{ INDEX_op_qemu_ld_i64, { "r", "r", "l", "l" } },
		{ INDEX_op_qemu_st_i32, { "s", "s", "s" } },
		{ INDEX_op_qemu_st_i64, { "s", "s", "s", "s" } },
		#endif

		{ INDEX_op_bswap16_i32, { "r", "r" } },

tcg/arm/tcg-target.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -85,7 +85,7 @@ extern bool use_idiv_instructions;
		#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
		#define TCG_TARGET_HAS_rem_i32 0

		#define TCG_TARGET_HAS_new_ldst 0
		#define TCG_TARGET_HAS_new_ldst 1

		extern bool tcg_target_deposit_valid(int ofs, int len);
		#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid