Commit 15e12add authored by David Hildenbrand's avatar David Hildenbrand Committed by Cornelia Huck
Browse files

s390x/tcg: Implement VECTOR STORE 



Properly probe the whole access first.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarDavid Hildenbrand <david@redhat.com>
Message-Id: <20190307121539.12842-29-david@redhat.com>
Signed-off-by: default avatarCornelia Huck <cohuck@redhat.com>
parent c5a7392c

target/s390x/insn-data.def

+2 −0
Original line number Diff line number Diff line
@@ -1034,6 +1034,8 @@ 
    F(0xe78d, VSEL,    VRR_e, V,   0, 0, 0, 0, vsel, 0, IF_VEC)

/* VECTOR SIGN EXTEND TO DOUBLEWORD */

    F(0xe75f, VSEG,    VRR_a, V,   0, 0, 0, 0, vseg, 0, IF_VEC)

/* VECTOR STORE */

    F(0xe70e, VST,     VRX,   V,   la2, 0, 0, 0, vst, 0, IF_VEC)



#ifndef CONFIG_USER_ONLY

/* COMPARE AND SWAP AND PURGE */

target/s390x/translate_vx.inc.c

+17 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, 
    }

}





static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,

                                    uint8_t es)

{
@@ -817,3 +818,19 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOps *o) 
    tcg_temp_free_i64(tmp);

    return DISAS_NEXT;

}



static DisasJumpType op_vst(DisasContext *s, DisasOps *o)

{

    TCGv_i64 tmp = tcg_const_i64(16);



    /* Probe write access before actually modifying memory */

    gen_helper_probe_write_access(cpu_env, o->addr1, tmp);



    read_vec_element_i64(tmp,  get_field(s->fields, v1), 0, ES_64);

    tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);

    gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);

    read_vec_element_i64(tmp,  get_field(s->fields, v1), 1, ES_64);

    tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);

    tcg_temp_free_i64(tmp);

    return DISAS_NEXT;

}