Commit 14fd0c31 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Enable FPU for Cortex-M4 and Cortex-M33 



Enable the FPU by default for the Cortex-M4 and Cortex-M33.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-27-peter.maydell@linaro.org
parent 956fe143

target/arm/cpu.c

+8 −0
Original line number Diff line number Diff line
@@ -1493,8 +1493,12 @@ static void cortex_m4_initfn(Object *obj) 
    set_feature(&cpu->env, ARM_FEATURE_M);

    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);

    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    cpu->midr = 0x410fc240; /* r0p0 */

    cpu->pmsav7_dregion = 8;

    cpu->isar.mvfr0 = 0x10110021;

    cpu->isar.mvfr1 = 0x11000011;

    cpu->isar.mvfr2 = 0x00000000;

    cpu->id_pfr0 = 0x00000030;

    cpu->id_pfr1 = 0x00000200;

    cpu->id_dfr0 = 0x00100000;
@@ -1521,9 +1525,13 @@ static void cortex_m33_initfn(Object *obj) 
    set_feature(&cpu->env, ARM_FEATURE_M_MAIN);

    set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);

    set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);

    set_feature(&cpu->env, ARM_FEATURE_VFP4);

    cpu->midr = 0x410fd213; /* r0p3 */

    cpu->pmsav7_dregion = 16;

    cpu->sau_sregion = 8;

    cpu->isar.mvfr0 = 0x10110021;

    cpu->isar.mvfr1 = 0x11000011;

    cpu->isar.mvfr2 = 0x00000040;

    cpu->id_pfr0 = 0x00000030;

    cpu->id_pfr1 = 0x00000210;

    cpu->id_dfr0 = 0x00200000;