Commit 14f92b0b authored by Aleksandar Markovic's avatar Aleksandar Markovic
Browse files

target/mips: Clean up handling of CP0 register 20 



Clean up handling of CP0 register 20.

Reviewed-by: default avatarAleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-22-git-send-email-aleksandar.markovic@rt-rk.com>
parent be274dc1

target/mips/translate.c

+4 −4
Original line number Diff line number Diff line
@@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
        break;

    case CP0_REGISTER_20:

        switch (sel) {

        case 0:

        case CP0_REG20__XCONTEXT:

#if defined(TARGET_MIPS64)

            check_insn(ctx, ISA_MIPS3);

            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
        break;

    case CP0_REGISTER_20:

        switch (sel) {

        case 0:

        case CP0_REG20__XCONTEXT:

#if defined(TARGET_MIPS64)

            check_insn(ctx, ISA_MIPS3);

            gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
        break;

    case CP0_REGISTER_20:

        switch (sel) {

        case 0:

        case CP0_REG20__XCONTEXT:

            check_insn(ctx, ISA_MIPS3);

            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));

            register_name = "XContext";
@@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
        break;

    case CP0_REGISTER_20:

        switch (sel) {

        case 0:

        case CP0_REG20__XCONTEXT:

            check_insn(ctx, ISA_MIPS3);

            gen_helper_mtc0_xcontext(cpu_env, arg);

            register_name = "XContext";