Commit 14c7d993 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160714' into staging 



target-arm queue:
 * add virtio-mmio transport base address to device path
   (avoid an assertion failure with multiple virtio-scsi-devices)
 * revert hw/ptimer commit 5a50307b which causes regressions on
   SPARC guests
 * use Neon to accelerate zero-page checking on AArch64 hosts
 * set the MPIDR for TCG to match how KVM does it (and fit with
   GICv2/GICv3 restrictions on SGI target lists)
 * add some missing AArch32 TLBI hypervisor TLB operations
 * m25p80: Fix QIOR/DIOR handling for Winbond
 * hw/misc: fix typo in Aspeed SCU hw-strap2 property name
 * ast2400: pretend DMAs are done for U-boot
 * ast2400: some minor code cleanups

# gpg: Signature made Thu 14 Jul 2016 17:21:30 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160714:
  ast2400: externalize revision numbers
  ast2400: pretend DMAs are done for U-boot
  ast2400: replace aspeed_smc_is_implemented()
  hw/misc: fix typo in Aspeed SCU hw-strap2 property name
  m25p80: Fix QIOR/DIOR handling for Winbond
  target-arm: Add missed AArch32 TLBI sytem registers
  hw/arm/virt: tcg: adjust MPIDR like KVM
  gic: provide defines for v2/v3 targetlist sizes
  target-arm: Use Neon for zero checking
  Revert "hw/ptimer: Perform counter wrap around if timer already expired"
  virtio-mmio: format transport base address in BusClass.get_dev_path

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 1c8e93fb 79a9f323

hw/arm/ast2400.c

+0 −2
Original line number Diff line number Diff line
@@ -34,8 +34,6 @@ 
#define AST2400_FMC_FLASH_BASE   0x20000000

#define AST2400_SPI_FLASH_BASE   0x30000000



#define AST2400_A0_SILICON_REV   0x02000303



static const int uart_irqs[] = { 9, 32, 33, 34, 10 };

static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };

hw/arm/virt.c

+24 −1
Original line number Diff line number Diff line
@@ -52,7 +52,8 @@ 
#include "hw/arm/sysbus-fdt.h"

#include "hw/platform-bus.h"

#include "hw/arm/fdt.h"

#include "hw/intc/arm_gic_common.h"

#include "hw/intc/arm_gic.h"

#include "hw/intc/arm_gicv3_common.h"

#include "kvm_arm.h"

#include "hw/smbios/smbios.h"

#include "qapi/visitor.h"
@@ -82,6 +83,7 @@ typedef struct VirtBoardInfo { 
typedef struct {

    MachineClass parent;

    VirtBoardInfo *daughterboard;

    bool disallow_affinity_adjustment;

} VirtMachineClass;



typedef struct {
@@ -1165,6 +1167,7 @@ void virt_guest_info_machine_done(Notifier *notifier, void *data) 
static void machvirt_init(MachineState *machine)

{

    VirtMachineState *vms = VIRT_MACHINE(machine);

    VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);

    qemu_irq pic[NUM_IRQS];

    MemoryRegion *sysmem = get_system_memory();

    MemoryRegion *secure_sysmem = NULL;
@@ -1181,6 +1184,7 @@ static void machvirt_init(MachineState *machine) 
    CPUClass *cc;

    Error *err = NULL;

    bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);

    uint8_t clustersz;



    if (!cpu_model) {

        cpu_model = "cortex-a15";
@@ -1226,8 +1230,10 @@ static void machvirt_init(MachineState *machine) 
     */

    if (gic_version == 3) {

        virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000;

        clustersz = GICV3_TARGETLIST_BITS;

    } else {

        virt_max_cpus = GIC_NCPU;

        clustersz = GIC_TARGETLIST_BITS;

    }



    if (max_cpus > virt_max_cpus) {
@@ -1281,6 +1287,20 @@ static void machvirt_init(MachineState *machine) 


    for (n = 0; n < smp_cpus; n++) {

        Object *cpuobj = object_new(typename);

        if (!vmc->disallow_affinity_adjustment) {

            /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the

             * GIC's target-list limitations. 32-bit KVM hosts currently

             * always create clusters of 4 CPUs, but that is expected to

             * change when they gain support for gicv3. When KVM is enabled

             * it will override the changes we make here, therefore our

             * purposes are to make TCG consistent (with 64-bit KVM hosts)

             * and to improve SGI efficiency.

             */

            uint8_t aff1 = n / clustersz;

            uint8_t aff0 = n % clustersz;

            object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0,

                                    "mp-affinity", NULL);

        }



        if (!vms->secure) {

            object_property_set_bool(cpuobj, false, "has_el3", NULL);
@@ -1507,7 +1527,10 @@ static void virt_2_6_instance_init(Object *obj) 


static void virt_machine_2_6_options(MachineClass *mc)

{

    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));



    virt_machine_2_7_options(mc);

    SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);

    vmc->disallow_affinity_adjustment = true;

}

DEFINE_VIRT_MACHINE(2, 6)

hw/block/m25p80.c

+4 −2
Original line number Diff line number Diff line
@@ -149,6 +149,7 @@ typedef struct FlashPartInfo { 
*/



#define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1

#define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1



static const FlashPartInfo known_devices[] = {

    /* Atmel -- some are (confusingly) marketed as "DataFlash" */
@@ -777,7 +778,7 @@ static void decode_dio_read_cmd(Flash *s) 
    /* Dummy cycles modeled with bytes writes instead of bits */

    switch (get_man(s)) {

    case MAN_WINBOND:

        s->needed_bytes += 8;

        s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;

        break;

    case MAN_SPANSION:

        s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
@@ -816,7 +817,8 @@ static void decode_qio_read_cmd(Flash *s) 
    /* Dummy cycles modeled with bytes writes instead of bits */

    switch (get_man(s)) {

    case MAN_WINBOND:

        s->needed_bytes += 8;

        s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;

        s->needed_bytes += 4;

        break;

    case MAN_SPANSION:

        s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;

hw/core/ptimer.c

+2 −7
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ uint64_t ptimer_get_count(ptimer_state *s) 
        bool oneshot = (s->enabled == 2);



        /* Figure out the current counter value.  */

        if (s->period == 0 || (expired && (oneshot || use_icount))) {

        if (expired) {

            /* Prevent timer underflowing if it should already have

               triggered.  */

            counter = 0;
@@ -120,7 +120,7 @@ uint64_t ptimer_get_count(ptimer_state *s) 
               backwards.

            */



            rem = expired ? now - next : next - now;

            rem = next - now;

            div = period;



            clz1 = clz64(rem);
@@ -140,11 +140,6 @@ uint64_t ptimer_get_count(ptimer_state *s) 
                    div += 1;

            }

            counter = rem / div;



            if (expired && counter != 0) {

                /* Wrap around periodic counter.  */

                counter = s->limit - (counter - 1) % s->limit;

            }

        }

    } else {

        counter = s->delta;

hw/misc/aspeed_scu.c

+2 −4
Original line number Diff line number Diff line
@@ -88,8 +88,6 @@ 
#define PROT_KEY_UNLOCK 0x1688A8A8

#define SCU_IO_REGION_SIZE 0x20000



#define AST2400_A0_SILICON_REV     0x02000303U



static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {

     [SYS_RST_CTRL]    = 0xFFCFFEDCU,

     [CLK_SEL]         = 0xF3F40000U,
@@ -212,7 +210,7 @@ static void aspeed_scu_reset(DeviceState *dev) 


static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };



static bool is_supported_silicon_rev(uint32_t silicon_rev)

bool is_supported_silicon_rev(uint32_t silicon_rev)

{

    int i;
@@ -255,7 +253,7 @@ static const VMStateDescription vmstate_aspeed_scu = { 
static Property aspeed_scu_properties[] = {

    DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),

    DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),

    DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap1, 0),

    DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),

    DEFINE_PROP_END_OF_LIST(),

};