Commit 143c30d4 authored by Moger, Babu's avatar Moger, Babu Committed by Eduardo Habkost
Browse files

i386: Add 2nd Generation AMD EPYC processors 

Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.

Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
               use extended performance counter support. It enables six
               programmable counters instead of four counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
wbnoinvd     : Write back and do not invalidate cache
ibpb         : Indirect Branch Prediction Barrier
amd-stibp    : Single Thread Indirect Branch Predictor
clwb         : Cache Line Write Back and Retain
xsaves       : XSAVES, XRSTORS and IA32_XSS support
rdpid        : Read Processor ID instruction support
umip         : User-Mode Instruction Prevention support

The  Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf



Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
6d61e3c32248 ("kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Message-Id: <157314966312.23828.17684821666338093910.stgit@naples-babu.amd.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent a16e8dbc

target/i386/cpu.c

+101 −1
Original line number Diff line number Diff line
@@ -1133,7 +1133,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            "clzero", NULL, "xsaveerptr", NULL,

            NULL, NULL, NULL, NULL,

            NULL, "wbnoinvd", NULL, NULL,

            "ibpb", NULL, NULL, NULL,

            "ibpb", NULL, NULL, "amd-stibp",

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
@@ -1798,6 +1798,56 @@ static CPUCaches epyc_cache_info = { 
    },

};



static CPUCaches epyc_rome_cache_info = {

    .l1d_cache = &(CPUCacheInfo) {

        .type = DATA_CACHE,

        .level = 1,

        .size = 32 * KiB,

        .line_size = 64,

        .associativity = 8,

        .partitions = 1,

        .sets = 64,

        .lines_per_tag = 1,

        .self_init = 1,

        .no_invd_sharing = true,

    },

    .l1i_cache = &(CPUCacheInfo) {

        .type = INSTRUCTION_CACHE,

        .level = 1,

        .size = 32 * KiB,

        .line_size = 64,

        .associativity = 8,

        .partitions = 1,

        .sets = 64,

        .lines_per_tag = 1,

        .self_init = 1,

        .no_invd_sharing = true,

    },

    .l2_cache = &(CPUCacheInfo) {

        .type = UNIFIED_CACHE,

        .level = 2,

        .size = 512 * KiB,

        .line_size = 64,

        .associativity = 8,

        .partitions = 1,

        .sets = 1024,

        .lines_per_tag = 1,

    },

    .l3_cache = &(CPUCacheInfo) {

        .type = UNIFIED_CACHE,

        .level = 3,

        .size = 16 * MiB,

        .line_size = 64,

        .associativity = 16,

        .partitions = 1,

        .sets = 16384,

        .lines_per_tag = 1,

        .self_init = true,

        .inclusive = true,

        .complex_indexing = true,

    },

};



/* The following VMX features are not supported by KVM and are left out in the

 * CPU definitions:

 *
@@ -4030,6 +4080,56 @@ static X86CPUDefinition builtin_x86_defs[] = { 
        .model_id = "Hygon Dhyana Processor",

        .cache_info = &epyc_cache_info,

    },

    {

        .name = "EPYC-Rome",

        .level = 0xd,

        .vendor = CPUID_VENDOR_AMD,

        .family = 23,

        .model = 49,

        .stepping = 0,

        .features[FEAT_1_EDX] =

            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |

            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |

            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |

            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |

            CPUID_VME | CPUID_FP87,

        .features[FEAT_1_ECX] =

            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |

            CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |

            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |

            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |

            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,

        .features[FEAT_8000_0001_EDX] =

            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |

            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |

            CPUID_EXT2_SYSCALL,

        .features[FEAT_8000_0001_ECX] =

            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |

            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |

            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |

            CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,

        .features[FEAT_8000_0008_EBX] =

            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |

            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |

            CPUID_8000_0008_EBX_STIBP,

        .features[FEAT_7_0_EBX] =

            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |

            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |

            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |

            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,

        .features[FEAT_7_0_ECX] =

            CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,

        .features[FEAT_XSAVE] =

            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |

            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,

        .features[FEAT_6_EAX] =

            CPUID_6_EAX_ARAT,

        .features[FEAT_SVM] =

            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,

        .xlevel = 0x8000001E,

        .model_id = "AMD EPYC-Rome Processor",

        .cache_info = &epyc_rome_cache_info,

    },

};



/* KVM-specific features that are automatically added/removed

target/i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -792,6 +792,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)

/* Indirect Branch Prediction Barrier */

#define CPUID_8000_0008_EBX_IBPB        (1U << 12)

/* Single Thread Indirect Branch Predictors */

#define CPUID_8000_0008_EBX_STIBP       (1U << 15)



#define CPUID_XSAVE_XSAVEOPT   (1U << 0)

#define CPUID_XSAVE_XSAVEC     (1U << 1)