Commit 14120108 authored by Julia Suvorova's avatar Julia Suvorova Committed by Peter Maydell
Browse files

target/arm: Allow ARMv6-M Thumb2 instructions 



ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.

This patch is required for future Cortex-M0 support.

Signed-off-by: default avatarJulia Suvorova <jusual@mail.ru>
Reviewed-by: default avatarStefan Hajnoczi <stefanha@redhat.com>
Message-id: 20180612204632.28780-1-jusual@mail.ru
[PMM: move armv6m_insn[] and armv6m_mask[] closer to
 point of use, and mark 'const'. Check for M-and-not-v7
 rather than M-and-6.]
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 1f871c5e

target/arm/translate.c

+38 −5
Original line number Diff line number Diff line
@@ -9965,7 +9965,8 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) 
     * end up actually treating this as two 16-bit insns, though,

     * if it's half of a bl/blx pair that might span a page boundary.

     */

    if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) {

    if (arm_dc_feature(s, ARM_FEATURE_THUMB2) ||

        arm_dc_feature(s, ARM_FEATURE_M)) {

        /* Thumb2 cores (including all M profile ones) always treat

         * 32-bit insns as 32-bit.

         */
@@ -10085,10 +10086,38 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 
    int conds;

    int logic_cc;



    /* The only 32 bit insn that's allowed for Thumb1 is the combined

     * BL/BLX prefix and suffix.

    /*

     * ARMv6-M supports a limited subset of Thumb2 instructions.

     * Other Thumb1 architectures allow only 32-bit

     * combined BL/BLX prefix and suffix.

     */

    if ((insn & 0xf800e800) != 0xf000e800) {

    if (arm_dc_feature(s, ARM_FEATURE_M) &&

        !arm_dc_feature(s, ARM_FEATURE_V7)) {

        int i;

        bool found = false;

        const uint32_t armv6m_insn[] = {0xf3808000 /* msr */,

                                        0xf3b08040 /* dsb */,

                                        0xf3b08050 /* dmb */,

                                        0xf3b08060 /* isb */,

                                        0xf3e08000 /* mrs */,

                                        0xf000d000 /* bl */};

        const uint32_t armv6m_mask[] = {0xffe0d000,

                                        0xfff0d0f0,

                                        0xfff0d0f0,

                                        0xfff0d0f0,

                                        0xffe0d000,

                                        0xf800d000};



        for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) {

            if ((insn & armv6m_mask[i]) == armv6m_insn[i]) {

                found = true;

                break;

            }

        }

        if (!found) {

            goto illegal_op;

        }

    } else if ((insn & 0xf800e800) != 0xf000e800)  {

        ARCH(6T2);

    }
@@ -11009,7 +11038,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 
                        }

                        break;

                    case 3: /* Special control operations.  */

                        ARCH(7);

                        if (!arm_dc_feature(s, ARM_FEATURE_V7) &&

                            !(arm_dc_feature(s, ARM_FEATURE_V6) &&

                              arm_dc_feature(s, ARM_FEATURE_M))) {

                            goto illegal_op;

                        }

                        op = (insn >> 4) & 0xf;

                        switch (op) {

                        case 2: /* clrex */