Commit 12fbf1a1 authored by Peter Maydell's avatar Peter Maydell
Browse files

hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions 



In many of the NVIC registers relating to interrupts, we
have to convert from a byte offset within a register set
into the number of the first interrupt which is affected.
We were getting this wrong for:
 * reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>,
   NVIC_IABR<n> -- in all these cases we were missing the "* 8"
   needed to convert from the byte offset to the interrupt number
   (since all these registers use one bit per interrupt)
 * writes of NVIC_IPR<n> had the opposite problem of a spurious
   "* 8" (since these registers use one byte per interrupt)

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180209165810.6668-9-peter.maydell@linaro.org
parent 6eb3a64e

hw/intc/armv7m_nvic.c

+4 −4
Original line number Diff line number Diff line
@@ -1724,7 +1724,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 
        /* fall through */

    case 0x180 ... 0x1bf: /* NVIC Clear enable */

        val = 0;

        startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */

        startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */



        for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {

            if (s->vectors[startvec + i].enabled &&
@@ -1738,7 +1738,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 
        /* fall through */

    case 0x280 ... 0x2bf: /* NVIC Clear pend */

        val = 0;

        startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */

        startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */

        for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {

            if (s->vectors[startvec + i].pending &&

                (attrs.secure || s->itns[startvec + i])) {
@@ -1748,7 +1748,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, 
        break;

    case 0x300 ... 0x33f: /* NVIC Active */

        val = 0;

        startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */

        startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */



        for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {

            if (s->vectors[startvec + i].active &&
@@ -1863,7 +1863,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
    case 0x300 ... 0x33f: /* NVIC Active */

        return MEMTX_OK; /* R/O */

    case 0x400 ... 0x5ef: /* NVIC Priority */

        startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */

        startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */



        for (i = 0; i < size && startvec + i < s->num_irq; i++) {

            if (attrs.secure || s->itns[startvec + i]) {