Loading hw/intc/xive.c +3 −3 Original line number Diff line number Diff line Loading @@ -321,7 +321,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* Loading Loading @@ -360,7 +360,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* Loading Loading @@ -1186,7 +1186,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; int ring; /* Loading hw/ppc/spapr_cpu_core.c +6 −1 Original line number Diff line number Diff line Loading @@ -194,7 +194,12 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); } qemu_unregister_reset(spapr_cpu_reset, cpu); if (cpu->intc) { object_unparent(cpu->intc); } if (cpu->tctx) { object_unparent(OBJECT(cpu->tctx)); } cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } Loading hw/ppc/spapr_irq.c +4 −4 Original line number Diff line number Diff line Loading @@ -315,7 +315,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon); xive_tctx_pic_print_info(cpu->tctx, mon); } spapr_xive_pic_print_info(spapr->xive, mon); Loading @@ -333,13 +333,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, return; } cpu->intc = obj; cpu->tctx = XIVE_TCTX(obj); /* * (TCG) Early setting the OS CAM line for hotplugged CPUs as they * don't beneficiate from the reset of the XIVE IRQ backend */ spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj)); spapr_xive_set_tctx_os_cam(cpu->tctx); } static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id) Loading @@ -355,7 +355,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) PowerPCCPU *cpu = POWERPC_CPU(cs); /* (TCG) Set the OS CAM line of the thread interrupt context. */ spapr_xive_set_tctx_os_cam(XIVE_TCTX(cpu->intc)); spapr_xive_set_tctx_os_cam(cpu->tctx); } } Loading target/ppc/cpu.h +2 −0 Original line number Diff line number Diff line Loading @@ -1177,6 +1177,7 @@ do { \ typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; typedef struct XiveTCTX XiveTCTX; /** * PowerPCCPU: Loading @@ -1196,6 +1197,7 @@ struct PowerPCCPU { uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; Object *intc; XiveTCTX *tctx; void *machine_data; int32_t node_id; /* NUMA node this CPU belongs to */ PPCHash64Options *hash64_opts; Loading Loading
hw/intc/xive.c +3 −3 Original line number Diff line number Diff line Loading @@ -321,7 +321,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* Loading Loading @@ -360,7 +360,7 @@ static void xive_tm_write(void *opaque, hwaddr offset, static uint64_t xive_tm_read(void *opaque, hwaddr offset, unsigned size) { PowerPCCPU *cpu = POWERPC_CPU(current_cpu); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; const XiveTmOp *xto; /* Loading Loading @@ -1186,7 +1186,7 @@ static bool xive_presenter_match(XiveRouter *xrtr, uint8_t format, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); XiveTCTX *tctx = XIVE_TCTX(cpu->intc); XiveTCTX *tctx = cpu->tctx; int ring; /* Loading
hw/ppc/spapr_cpu_core.c +6 −1 Original line number Diff line number Diff line Loading @@ -194,7 +194,12 @@ static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc) vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data); } qemu_unregister_reset(spapr_cpu_reset, cpu); if (cpu->intc) { object_unparent(cpu->intc); } if (cpu->tctx) { object_unparent(OBJECT(cpu->tctx)); } cpu_remove_sync(CPU(cpu)); object_unparent(OBJECT(cpu)); } Loading
hw/ppc/spapr_irq.c +4 −4 Original line number Diff line number Diff line Loading @@ -315,7 +315,7 @@ static void spapr_irq_print_info_xive(sPAPRMachineState *spapr, CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); xive_tctx_pic_print_info(XIVE_TCTX(cpu->intc), mon); xive_tctx_pic_print_info(cpu->tctx, mon); } spapr_xive_pic_print_info(spapr->xive, mon); Loading @@ -333,13 +333,13 @@ static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr, return; } cpu->intc = obj; cpu->tctx = XIVE_TCTX(obj); /* * (TCG) Early setting the OS CAM line for hotplugged CPUs as they * don't beneficiate from the reset of the XIVE IRQ backend */ spapr_xive_set_tctx_os_cam(XIVE_TCTX(obj)); spapr_xive_set_tctx_os_cam(cpu->tctx); } static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id) Loading @@ -355,7 +355,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp) PowerPCCPU *cpu = POWERPC_CPU(cs); /* (TCG) Set the OS CAM line of the thread interrupt context. */ spapr_xive_set_tctx_os_cam(XIVE_TCTX(cpu->intc)); spapr_xive_set_tctx_os_cam(cpu->tctx); } } Loading
target/ppc/cpu.h +2 −0 Original line number Diff line number Diff line Loading @@ -1177,6 +1177,7 @@ do { \ typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; typedef struct XiveTCTX XiveTCTX; /** * PowerPCCPU: Loading @@ -1196,6 +1197,7 @@ struct PowerPCCPU { uint32_t compat_pvr; PPCVirtualHypervisor *vhyp; Object *intc; XiveTCTX *tctx; void *machine_data; int32_t node_id; /* NUMA node this CPU belongs to */ PPCHash64Options *hash64_opts; Loading