Commit 11f4e8f8 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg: Remove TCGV_EQUAL* 



When we used structures for TCGv_*, we needed a macro in order to
perform a comparison.  Now that we use pointers, this is just clutter.

Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarEmilio G. Cota <cota@braap.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent dc41aa7d

target/cris/translate.c

+3 −3
Original line number Diff line number Diff line
@@ -839,7 +839,7 @@ static void cris_alu(DisasContext *dc, int op, 
        }

        tcg_gen_or_tl(d, d, tmp);

    }

    if (!TCGV_EQUAL(tmp, d)) {

    if (tmp != d) {

        tcg_temp_free(tmp);

    }

}
@@ -1162,7 +1162,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size) 
        tcg_gen_ext8s_i32(d, s);

    } else if (size == 2) {

        tcg_gen_ext16s_i32(d, s);

    } else if (!TCGV_EQUAL(d, s)) {

    } else {

        tcg_gen_mov_tl(d, s);

    }

}
@@ -1173,7 +1173,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size) 
        tcg_gen_ext8u_i32(d, s);

    } else if (size == 2) {

        tcg_gen_ext16u_i32(d, s);

    } else if (!TCGV_EQUAL(d, s)) {

    } else {

        tcg_gen_mov_tl(d, s);

    }

}

target/i386/translate.c

+3 −3
Original line number Diff line number Diff line
@@ -742,7 +742,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) 
        size = s->cc_op - CC_OP_SUBB;

        t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);

        /* If no temporary was used, be careful not to alias t1 and t0.  */

        t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;

        t0 = t1 == cpu_cc_src ? cpu_tmp0 : reg;

        tcg_gen_mov_tl(t0, cpu_cc_srcT);

        gen_extu(size, t0);

        goto add_sub;
@@ -951,7 +951,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) 
            break;

        case JCC_L:

            gen_compute_eflags(s);

            if (TCGV_EQUAL(reg, cpu_cc_src)) {

            if (reg == cpu_cc_src) {

                reg = cpu_tmp0;

            }

            tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
@@ -962,7 +962,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) 
        default:

        case JCC_LE:

            gen_compute_eflags(s);

            if (TCGV_EQUAL(reg, cpu_cc_src)) {

            if (reg == cpu_cc_src) {

                reg = cpu_tmp0;

            }

            tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */

target/m68k/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ static TCGv_i64 cpu_macc[4]; 
#define QREG_SP         get_areg(s, 7)



static TCGv NULL_QREG;

#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))

#define IS_NULL_QREG(t) (t == NULL_QREG)

/* Used to distinguish stores from bad addressing modes.  */

static TCGv store_dummy;

target/ppc/translate.c

+2 −2
Original line number Diff line number Diff line
@@ -902,7 +902,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, 
        gen_set_Rc0(ctx, t0);

    }



    if (!TCGV_EQUAL(t0, ret)) {

    if (t0 != ret) {

        tcg_gen_mov_tl(ret, t0);

        tcg_temp_free(t0);

    }
@@ -1438,7 +1438,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, 
        gen_set_Rc0(ctx, t0);

    }



    if (!TCGV_EQUAL(t0, ret)) {

    if (t0 != ret) {

        tcg_gen_mov_tl(ret, t0);

        tcg_temp_free(t0);

    }

tcg/tcg-op.h

+2 −4
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ static inline void tcg_gen_discard_i32(TCGv_i32 arg) 


static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)

{

    if (!TCGV_EQUAL_I32(ret, arg)) {

    if (ret != arg) {

        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);

    }

}
@@ -522,7 +522,7 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg) 


static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)

{

    if (!TCGV_EQUAL_I64(ret, arg)) {

    if (ret != arg) {

        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);

    }

}
@@ -809,7 +809,6 @@ void tcg_gen_lookup_and_goto_ptr(void); 
#define tcg_temp_free tcg_temp_free_i32

#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)

#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)

#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)

#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32

#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32

#else
@@ -820,7 +819,6 @@ void tcg_gen_lookup_and_goto_ptr(void); 
#define tcg_temp_free tcg_temp_free_i64

#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)

#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)

#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)

#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64

#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64

#endif