Commit 11d7870b authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Fix SVE system register access checks 



Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check
produced by the flag already includes fp_access_check.  If
we also check ARM_CP_FPU the double fp_access_check asserts.

Reported-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180629001538.11415-3-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 7e8fafbf

target/arm/helper.c

+4 −4
Original line number Diff line number Diff line
@@ -4414,7 +4414,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
static const ARMCPRegInfo zcr_el1_reginfo = {

    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .access = PL1_RW, .type = ARM_CP_SVE,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),

    .writefn = zcr_write, .raw_writefn = raw_write

};
@@ -4422,7 +4422,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = { 
static const ARMCPRegInfo zcr_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .access = PL2_RW, .type = ARM_CP_SVE,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),

    .writefn = zcr_write, .raw_writefn = raw_write

};
@@ -4430,14 +4430,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = { 
static const ARMCPRegInfo zcr_no_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .access = PL2_RW, .type = ARM_CP_SVE,

    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore

};



static const ARMCPRegInfo zcr_el3_reginfo = {

    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .access = PL3_RW, .type = ARM_CP_SVE,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),

    .writefn = zcr_write, .raw_writefn = raw_write

};

target/arm/translate-a64.c

+2 −3
Original line number Diff line number Diff line
@@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, 
    default:

        break;

    }

    if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {

        return;

    }

    if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {

        return;

    } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {

        return;

    }



    if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {