Commit 0f8d06f1 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Conditionalize some asserts on aarch32 support 



When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Tested-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 20181102102025.3546-1-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 5e9fcbd7

target/arm/cpu.c

+13 −2
Original line number Diff line number Diff line
@@ -774,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
    CPUARMState *env = &cpu->env;

    int pagebits;

    Error *local_err = NULL;

    bool no_aa32 = false;



    /* If we needed to query the host kernel for the CPU features

     * then it's possible that might have failed in the initfn, but
@@ -820,6 +821,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
            set_feature(env, ARM_FEATURE_V7VE);

        }

    }



    /*

     * There exist AArch64 cpus without AArch32 support.  When KVM

     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.

     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.

     */

    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {

        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);

    }



    if (arm_feature(env, ARM_FEATURE_V7VE)) {

        /* v7 Virtualization Extensions. In real hardware this implies

         * EL2 and also the presence of the Security Extensions.
@@ -829,7 +840,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the

         * Security Extensions is ARM_FEATURE_EL3.

         */

        assert(cpu_isar_feature(arm_div, cpu));

        assert(no_aa32 || cpu_isar_feature(arm_div, cpu));

        set_feature(env, ARM_FEATURE_LPAE);

        set_feature(env, ARM_FEATURE_V7);

    }
@@ -855,7 +866,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
    if (arm_feature(env, ARM_FEATURE_V6)) {

        set_feature(env, ARM_FEATURE_V5);

        if (!arm_feature(env, ARM_FEATURE_M)) {

            assert(cpu_isar_feature(jazelle, cpu));

            assert(no_aa32 || cpu_isar_feature(jazelle, cpu));

            set_feature(env, ARM_FEATURE_AUXCR);

        }

    }

target/arm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -3296,6 +3296,11 @@ static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 
    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;

}



static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;

}



static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;