Commit 0f72559f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161227' into staging 



target-arm queue:
 * add VBAR support to ARM1176 CPUs
 * hw/i2c: add NULL check to i2c slave init callbacks
 * pxa2xx.c: fix trailing whitespace
 * aspeed: various cleanups
 * aspeed: add romulus-bmc board
 * virt: add 2.9 machine type
 * gicv3: don't signal Pending+Active interrupts to CPU
 * gicv3: fix incorrect usage of fieldoffset
 * arm: log AArch64 exception returns
 * gicv3: fix aff3 field in typer register
 * aarch64: fix ldst_single_struct on BE hosts
 * aarch64: fix vec_reg_offset on BE hosts
 * arm: fix Cortex-A8 MVFR1 register value
 * cadence_uart: check if receiver timeout counter disabled
 * cadence_uart: check register values on migration

# gpg: Signature made Tue 27 Dec 2016 15:19:26 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20161227: (25 commits)
  target-arm: Add VBAR support to ARM1176 CPUs
  hw/i2c: Add a NULL check for i2c slave init callbacks
  hw/arm: remove trailing whitespace
  aspeed/smc: set the number of flash modules for the FMC controller
  aspeed/smc: improve segment register support
  aspeed/scu: fix SCU region size
  aspeed: change SoC revision of the palmetto-bmc machine
  aspeed: add the definitions for the AST2400 A1 SoC
  aspeed: add a memory region for SRAM
  aspeed: add support for the romulus-bmc board
  aspeed: extend the board configuration with flash models
  aspeed: attach the second SPI controller object to the SoC
  aspeed: remove cannot_destroy_with_object_finalize_yet
  aspeed: QOMify the CPU object and attach it to the SoC
  m25p80: add support for the mx66l1g45g
  hw/arm/virt: add 2.9 machine type
  hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU
  hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset
  target-arm: Log AArch64 exception returns
  hw/intc/arm_gicv3_common: fix aff3 in typer
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents e5fdf663 91db4642

hw/arm/aspeed.c

+66 −4
Original line number Diff line number Diff line
@@ -34,13 +34,18 @@ typedef struct AspeedBoardState { 
typedef struct AspeedBoardConfig {

    const char *soc_name;

    uint32_t hw_strap1;

    const char *fmc_model;

    const char *spi_model;

    uint32_t num_cs;

} AspeedBoardConfig;



enum {

    PALMETTO_BMC,

    AST2500_EVB,

    ROMULUS_BMC,

};



/* Palmetto hardware value: 0x120CE416 */

#define PALMETTO_BMC_HW_STRAP1 (                                        \

        SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) |               \

        SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
@@ -54,6 +59,7 @@ enum { 
        SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \

        SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))



/* AST2500 evb hardware value: 0xF100C2E6 */

#define AST2500_EVB_HW_STRAP1 ((                                        \

        AST2500_HW_STRAP1_DEFAULTS |                                    \

        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
@@ -64,9 +70,38 @@ enum { 
        SCU_HW_STRAP_MAC0_RGMII) &                                      \

        ~SCU_HW_STRAP_2ND_BOOT_WDT)



/* Romulus hardware value: 0xF10AD206 */

#define ROMULUS_BMC_HW_STRAP1 (                                         \

        AST2500_HW_STRAP1_DEFAULTS |                                    \

        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \

        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \

        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \

        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \

        SCU_AST2500_HW_STRAP_ACPI_ENABLE |                              \

        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))



static const AspeedBoardConfig aspeed_boards[] = {

    [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },

    [AST2500_EVB]  = { "ast2500-a1", AST2500_EVB_HW_STRAP1 },

    [PALMETTO_BMC] = {

        .soc_name  = "ast2400-a1",

        .hw_strap1 = PALMETTO_BMC_HW_STRAP1,

        .fmc_model = "n25q256a",

        .spi_model = "mx25l25635e",

        .num_cs    = 1,

    },

    [AST2500_EVB]  = {

        .soc_name  = "ast2500-a1",

        .hw_strap1 = AST2500_EVB_HW_STRAP1,

        .fmc_model = "n25q256a",

        .spi_model = "mx25l25635e",

        .num_cs    = 1,

    },

    [ROMULUS_BMC]  = {

        .soc_name  = "ast2500-a1",

        .hw_strap1 = ROMULUS_BMC_HW_STRAP1,

        .fmc_model = "n25q256a",

        .spi_model = "mx66l1g45g",

        .num_cs    = 2,

    },

};



static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
@@ -112,6 +147,8 @@ static void aspeed_board_init(MachineState *machine, 
                           &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",

                            &error_abort);

    object_property_set_int(OBJECT(&bmc->soc), cfg->num_cs, "num-cs",

                            &error_abort);

    object_property_set_bool(OBJECT(&bmc->soc), true, "realized",

                             &error_abort);
@@ -128,8 +165,8 @@ static void aspeed_board_init(MachineState *machine, 
    object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),

                                   &error_abort);



    aspeed_board_init_flashes(&bmc->soc.fmc, "n25q256a", &error_abort);

    aspeed_board_init_flashes(&bmc->soc.spi[0], "mx25l25635e", &error_abort);

    aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);

    aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);



    aspeed_board_binfo.kernel_filename = machine->kernel_filename;

    aspeed_board_binfo.initrd_filename = machine->initrd_filename;
@@ -188,10 +225,35 @@ static const TypeInfo ast2500_evb_type = { 
    .class_init = ast2500_evb_class_init,

};



static void romulus_bmc_init(MachineState *machine)

{

    aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);

}



static void romulus_bmc_class_init(ObjectClass *oc, void *data)

{

    MachineClass *mc = MACHINE_CLASS(oc);



    mc->desc = "OpenPOWER Romulus BMC (ARM1176)";

    mc->init = romulus_bmc_init;

    mc->max_cpus = 1;

    mc->no_sdcard = 1;

    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

}



static const TypeInfo romulus_bmc_type = {

    .name = MACHINE_TYPE_NAME("romulus-bmc"),

    .parent = TYPE_MACHINE,

    .class_init = romulus_bmc_class_init,

};



static void aspeed_machine_init(void)

{

    type_register_static(&palmetto_bmc_type);

    type_register_static(&ast2500_evb_type);

    type_register_static(&romulus_bmc_type);

}



type_init(aspeed_machine_init)

hw/arm/aspeed_soc.c

+72 −23
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#define ASPEED_SOC_VIC_BASE         0x1E6C0000

#define ASPEED_SOC_SDMC_BASE        0x1E6E0000

#define ASPEED_SOC_SCU_BASE         0x1E6E2000

#define ASPEED_SOC_SRAM_BASE        0x1E720000

#define ASPEED_SOC_TIMER_BASE       0x1E782000

#define ASPEED_SOC_I2C_BASE         0x1E78A000
@@ -47,15 +48,47 @@ static const char *aspeed_soc_ast2500_typenames[] = { 
    "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };



static const AspeedSoCInfo aspeed_socs[] = {

    { "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,

      1, aspeed_soc_ast2400_spi_bases,

      "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },

    { "ast2400",    "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,

      1, aspeed_soc_ast2400_spi_bases,

     "aspeed.smc.fmc", aspeed_soc_ast2400_typenames },

    { "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,

      2, aspeed_soc_ast2500_spi_bases,

      "aspeed.smc.ast2500-fmc", aspeed_soc_ast2500_typenames },

    {

        .name         = "ast2400-a0",

        .cpu_model    = "arm926",

        .silicon_rev  = AST2400_A0_SILICON_REV,

        .sdram_base   = AST2400_SDRAM_BASE,

        .sram_size    = 0x8000,

        .spis_num     = 1,

        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

    }, {

        .name         = "ast2400-a1",

        .cpu_model    = "arm926",

        .silicon_rev  = AST2400_A1_SILICON_REV,

        .sdram_base   = AST2400_SDRAM_BASE,

        .sram_size    = 0x8000,

        .spis_num     = 1,

        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

    }, {

        .name         = "ast2400",

        .cpu_model    = "arm926",

        .silicon_rev  = AST2400_A0_SILICON_REV,

        .sdram_base   = AST2400_SDRAM_BASE,

        .sram_size    = 0x8000,

        .spis_num     = 1,

        .spi_bases    = aspeed_soc_ast2400_spi_bases,

        .fmc_typename = "aspeed.smc.fmc",

        .spi_typename = aspeed_soc_ast2400_typenames,

    }, {

        .name         = "ast2500-a1",

        .cpu_model    = "arm1176",

        .silicon_rev  = AST2500_A1_SILICON_REV,

        .sdram_base   = AST2500_SDRAM_BASE,

        .sram_size    = 0x9000,

        .spis_num     = 2,

        .spi_bases    = aspeed_soc_ast2500_spi_bases,

        .fmc_typename = "aspeed.smc.ast2500-fmc",

        .spi_typename = aspeed_soc_ast2500_typenames,

    },

};



/*
@@ -87,9 +120,13 @@ static void aspeed_soc_init(Object *obj) 
{

    AspeedSoCState *s = ASPEED_SOC(obj);

    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);

    char *cpu_typename;

    int i;



    s->cpu = cpu_arm_init(sc->info->cpu_model);

    cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);

    object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);

    object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);

    g_free(cpu_typename);



    object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);

    object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
@@ -116,11 +153,13 @@ static void aspeed_soc_init(Object *obj) 
    object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);

    object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);

    qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());

    object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",

                              &error_abort);



    for (i = 0; i < sc->info->spis_num; i++) {

        object_initialize(&s->spi[i], sizeof(s->spi[i]),

                          sc->info->spi_typename[i]);

        object_property_add_child(obj, "spi", OBJECT(&s->spi[i]), NULL);

        object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);

        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());

    }
@@ -146,6 +185,24 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    memory_region_add_subregion_overlap(get_system_memory(),

                                        ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);



    /* CPU */

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }



    /* SRAM */

    memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",

                           sc->info->sram_size, &err);

    if (err) {

        error_propagate(errp, err);

        return;

    }

    vmstate_register_ram_global(&s->sram);

    memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,

                                &s->sram);



    /* VIC */

    object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);

    if (err) {
@@ -154,9 +211,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,

                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,

                       qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));

                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));



    /* Timer */

    object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
@@ -195,10 +252,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) 
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,

                       qdev_get_gpio_in(DEVICE(&s->vic), 12));



    /* FMC */

    object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);

    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);

    error_propagate(&err, local_err);

    /* FMC, The number of CS is set at the board level */

    object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);

    if (err) {

        error_propagate(errp, err);

        return;
@@ -240,12 +295,6 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) 


    sc->info = (AspeedSoCInfo *) data;

    dc->realize = aspeed_soc_realize;



    /*

     * Reason: creates an ARM CPU, thus use after free(), see

     * arm_cpu_class_init()

     */

    dc->cannot_destroy_with_object_finalize_yet = true;

}



static const TypeInfo aspeed_soc_type_info = {

hw/arm/pxa2xx.c

+1 −8
Original line number Diff line number Diff line
@@ -1449,17 +1449,10 @@ static const VMStateDescription vmstate_pxa2xx_i2c = { 
    }

};



static int pxa2xx_i2c_slave_init(I2CSlave *i2c)

{

    /* Nothing to do.  */

    return 0;

}



static void pxa2xx_i2c_slave_class_init(ObjectClass *klass, void *data)

{

    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);



    k->init = pxa2xx_i2c_slave_init;

    k->event = pxa2xx_i2c_event;

    k->recv = pxa2xx_i2c_rx;

    k->send = pxa2xx_i2c_tx;

hw/arm/tosa.c

+0 −7
Original line number Diff line number Diff line
@@ -202,12 +202,6 @@ static int tosa_dac_recv(I2CSlave *s) 
    return -1;

}



static int tosa_dac_init(I2CSlave *i2c)

{

    /* Nothing to do.  */

    return 0;

}



static void tosa_tg_init(PXA2xxState *cpu)

{

    I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
@@ -275,7 +269,6 @@ static void tosa_dac_class_init(ObjectClass *klass, void *data) 
{

    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);



    k->init = tosa_dac_init;

    k->event = tosa_dac_event;

    k->recv = tosa_dac_recv;

    k->send = tosa_dac_send;

hw/arm/virt.c

+17 −2
Original line number Diff line number Diff line
@@ -1525,7 +1525,7 @@ static void machvirt_machine_init(void) 
}

type_init(machvirt_machine_init);



static void virt_2_8_instance_init(Object *obj)

static void virt_2_9_instance_init(Object *obj)

{

    VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -1558,10 +1558,25 @@ static void virt_2_8_instance_init(Object *obj) 
                                    "Valid values are 2, 3 and host", NULL);

}



static void virt_machine_2_9_options(MachineClass *mc)

{

}

DEFINE_VIRT_MACHINE_AS_LATEST(2, 9)



#define VIRT_COMPAT_2_8 \

    HW_COMPAT_2_8



static void virt_2_8_instance_init(Object *obj)

{

    virt_2_9_instance_init(obj);

}



static void virt_machine_2_8_options(MachineClass *mc)

{

    virt_machine_2_9_options(mc);

    SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_8);

}

DEFINE_VIRT_MACHINE_AS_LATEST(2, 8)

DEFINE_VIRT_MACHINE(2, 8)



#define VIRT_COMPAT_2_7 \

    HW_COMPAT_2_7