target-mips: QOM'ify CPU (0f71a709) · Commits · SUMMER2020 / students / proj-2021291

Makefile.target

+3 −0

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		@@ -98,6 +98,9 @@ libobj-$(TARGET_CRIS) += cpu.o
		libobj-$(TARGET_LM32) += cpu.o
		libobj-$(TARGET_M68K) += cpu.o
		libobj-$(TARGET_MICROBLAZE) += cpu.o
		ifeq ($(TARGET_BASE_ARCH), mips)
		libobj-y += cpu.o
		endif
		libobj-$(TARGET_S390X) += cpu.o
		libobj-$(TARGET_SH4) += cpu.o
		ifeq ($(TARGET_BASE_ARCH), sparc)

target-mips/cpu-qom.h

0 → 100644

+74 −0

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		/*
		* QEMU MIPS CPU
		*
		* Copyright (c) 2012 SUSE LINUX Products GmbH
		*
		* This library is free software; you can redistribute it and/or
		* modify it under the terms of the GNU Lesser General Public
		* License as published by the Free Software Foundation; either
		* version 2.1 of the License, or (at your option) any later version.
		*
		* This library is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* Lesser General Public License for more details.
		*
		* You should have received a copy of the GNU Lesser General Public
		* License along with this library; if not, see
		* <http://www.gnu.org/licenses/lgpl-2.1.html>
		*/
		#ifndef QEMU_MIPS_CPU_QOM_H
		#define QEMU_MIPS_CPU_QOM_H

		#include "qemu/cpu.h"

		#ifdef TARGET_MIPS64
		#define TYPE_MIPS_CPU "mips64-cpu"
		#else
		#define TYPE_MIPS_CPU "mips-cpu"
		#endif

		#define MIPS_CPU_CLASS(klass) \
		OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
		#define MIPS_CPU(obj) \
		OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
		#define MIPS_CPU_GET_CLASS(obj) \
		OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)

		/**
		* MIPSCPUClass:
		* @parent_reset: The parent class' reset handler.
		*
		* A MIPS CPU model.
		*/
		typedef struct MIPSCPUClass {
		/< private >/
		CPUClass parent_class;
		/< public >/

		void (parent_reset)(CPUState cpu);
		} MIPSCPUClass;

		/**
		* MIPSCPU:
		* @env: #CPUMIPSState
		*
		* A MIPS CPU.
		*/
		typedef struct MIPSCPU {
		/< private >/
		CPUState parent_obj;
		/< public >/

		CPUMIPSState env;
		} MIPSCPU;

		static inline MIPSCPU mips_env_get_cpu(CPUMIPSState env)
		{
		return MIPS_CPU(container_of(env, MIPSCPU, env));
		}

		#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))


		#endif

target-mips/cpu.c

0 → 100644

+60 −0

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		/*
		* QEMU MIPS CPU
		*
		* Copyright (c) 2012 SUSE LINUX Products GmbH
		*
		* This library is free software; you can redistribute it and/or
		* modify it under the terms of the GNU Lesser General Public
		* License as published by the Free Software Foundation; either
		* version 2.1 of the License, or (at your option) any later version.
		*
		* This library is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* Lesser General Public License for more details.
		*
		* You should have received a copy of the GNU Lesser General Public
		* License along with this library; if not, see
		* <http://www.gnu.org/licenses/lgpl-2.1.html>
		*/

		#include "cpu.h"
		#include "qemu-common.h"


		/* CPUClass::reset() */
		static void mips_cpu_reset(CPUState *s)
		{
		MIPSCPU *cpu = MIPS_CPU(s);
		MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
		CPUMIPSState *env = &cpu->env;

		mcc->parent_reset(s);

		cpu_state_reset(env);
		}

		static void mips_cpu_class_init(ObjectClass c, void data)
		{
		MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
		CPUClass *cc = CPU_CLASS(c);

		mcc->parent_reset = cc->reset;
		cc->reset = mips_cpu_reset;
		}

		static const TypeInfo mips_cpu_type_info = {
		.name = TYPE_MIPS_CPU,
		.parent = TYPE_CPU,
		.instance_size = sizeof(MIPSCPU),
		.abstract = false,
		.class_size = sizeof(MIPSCPUClass),
		.class_init = mips_cpu_class_init,
		};

		static void mips_cpu_register_types(void)
		{
		type_register_static(&mips_cpu_type_info);
		}

		type_init(mips_cpu_register_types)

target-mips/cpu.h

+2 −0

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		@@ -483,6 +483,8 @@ struct CPUMIPSState {
		struct QEMUTimer timer; / Internal timer */
		};

		#include "cpu-qom.h"

		#if !defined(CONFIG_USER_ONLY)
		int no_mmu_map_address (CPUMIPSState env, target_phys_addr_t physical, int *prot,
		target_ulong address, int rw, int access_type);

target-mips/translate.c

+3 −1

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		@@ -12691,13 +12691,15 @@ static void mips_tcg_init(void)

		CPUMIPSState cpu_mips_init (const char cpu_model)
		{
		MIPSCPU *cpu;
		CPUMIPSState *env;
		const mips_def_t *def;

		def = cpu_mips_find_by_name(cpu_model);
		if (!def)
		return NULL;
		env = g_malloc0(sizeof(CPUMIPSState));
		cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
		env = &cpu->env;
		env->cpu_model = def;
		env->cpu_model_str = cpu_model;