Merge remote-tracking branch 'remotes/artyom/tags/pull-sun4v-20170118' into staging (0f6bcf68) · Commits · SUMMER2020 / students / proj-2021291

MAINTAINERS

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		@@ -725,6 +725,13 @@ S: Maintained
		F: hw/sparc64/sun4u.c
		F: pc-bios/openbios-sparc64

		Sun4v
		M: Artyom Tarasenko <atar4qemu@gmail.com>
		S: Maintained
		F: hw/sparc64/sun4v.c
		F: hw/timer/sun4v-rtc.c
		F: include/hw/timer/sun4v-rtc.h

		Leon3
		M: Fabien Chouteau <chouteau@adacore.com>
		S: Maintained

default-configs/sparc64-softmmu.mak

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		@@ -13,3 +13,5 @@ CONFIG_IDE_CMD646=y
		CONFIG_PCI_APB=y
		CONFIG_MC146818RTC=y
		CONFIG_ISA_TESTDEV=y
		CONFIG_EMPTY_SLOT=y
		CONFIG_SUN4V_RTC=y

hw/sparc64/Makefile.objs

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		obj-y += sparc64.o
		obj-y += sun4u.o
		obj-y += niagara.o
		No newline at end of file

hw/sparc64/niagara.c

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		/*
		* QEMU Sun4v/Niagara System Emulator
		*
		* Copyright (c) 2016 Artyom Tarasenko
		*
		* Permission is hereby granted, free of charge, to any person obtaining a copy
		* of this software and associated documentation files (the "Software"), to deal
		* in the Software without restriction, including without limitation the rights
		* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
		* copies of the Software, and to permit persons to whom the Software is
		* furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
		* THE SOFTWARE.
		*/

		#include "qemu/osdep.h"
		#include "qapi/error.h"
		#include "qemu-common.h"
		#include "cpu.h"
		#include "hw/hw.h"
		#include "hw/boards.h"
		#include "hw/char/serial.h"
		#include "hw/empty_slot.h"
		#include "hw/loader.h"
		#include "hw/sparc/sparc64.h"
		#include "hw/timer/sun4v-rtc.h"
		#include "exec/address-spaces.h"
		#include "sysemu/block-backend.h"


		typedef struct NiagaraBoardState {
		MemoryRegion hv_ram;
		MemoryRegion partition_ram;
		MemoryRegion nvram;
		MemoryRegion md_rom;
		MemoryRegion hv_rom;
		MemoryRegion vdisk_ram;
		MemoryRegion prom;
		} NiagaraBoardState;

		#define NIAGARA_HV_RAM_BASE 0x100000ULL
		#define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */

		#define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL

		#define NIAGARA_UART_BASE 0x1f10000000ULL

		#define NIAGARA_NVRAM_BASE 0x1f11000000ULL
		#define NIAGARA_NVRAM_SIZE 0x2000

		#define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
		#define NIAGARA_MD_ROM_SIZE 0x2000

		#define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
		#define NIAGARA_HV_ROM_SIZE 0x2000

		#define NIAGARA_IOBBASE 0x9800000000ULL
		#define NIAGARA_IOBSIZE 0x0100000000ULL

		#define NIAGARA_VDISK_BASE 0x1f40000000ULL
		#define NIAGARA_RTC_BASE 0xfff0c1fff8ULL
		#define NIAGARA_UART_BASE 0x1f10000000ULL

		/* Firmware layout
		*
		* \|------------------\|
		* \| openboot.bin \|
		* \|------------------\| PROM_ADDR + OBP_OFFSET
		* \| q.bin \|
		* \|------------------\| PROM_ADDR + Q_OFFSET
		* \| reset.bin \|
		* \|------------------\| PROM_ADDR
		*/
		#define NIAGARA_PROM_BASE 0xfff0000000ULL
		#define NIAGARA_Q_OFFSET 0x10000ULL
		#define NIAGARA_OBP_OFFSET 0x80000ULL
		#define PROM_SIZE_MAX (4 * 1024 * 1024)

		/* Niagara hardware initialisation */
		static void niagara_init(MachineState *machine)
		{
		NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
		DriveInfo *dinfo = drive_get_next(IF_PFLASH);
		MemoryRegion *sysmem = get_system_memory();

		/* init CPUs */
		sparc64_cpu_devinit(machine->cpu_model, "Sun UltraSparc T1",
		NIAGARA_PROM_BASE);
		/* set up devices */
		memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
		NIAGARA_HV_RAM_SIZE);
		memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);

		memory_region_allocate_system_memory(&s->partition_ram, NULL,
		"sun4v-partition.ram",
		machine->ram_size);
		memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
		&s->partition_ram);

		memory_region_allocate_system_memory(&s->nvram, NULL,
		"sun4v.nvram", NIAGARA_NVRAM_SIZE);
		memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
		memory_region_allocate_system_memory(&s->md_rom, NULL,
		"sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
		memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
		memory_region_allocate_system_memory(&s->hv_rom, NULL,
		"sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
		memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
		memory_region_allocate_system_memory(&s->prom, NULL,
		"sun4v.prom", PROM_SIZE_MAX);
		memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);

		rom_add_file_fixed("nvram1", NIAGARA_NVRAM_BASE, -1);
		rom_add_file_fixed("1up-md.bin", NIAGARA_MD_ROM_BASE, -1);
		rom_add_file_fixed("1up-hv.bin", NIAGARA_HV_ROM_BASE, -1);

		rom_add_file_fixed("reset.bin", NIAGARA_PROM_BASE, -1);
		rom_add_file_fixed("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET, -1);
		rom_add_file_fixed("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET,
		-1);

		/* the virtual ramdisk is kind of initrd, but it resides
		outside of the partition RAM */
		if (dinfo) {
		BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
		int size = blk_getlength(blk);
		if (size > 0) {
		memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
		"sun4v_vdisk.ram", size);
		memory_region_add_subregion(get_system_memory(),
		NIAGARA_VDISK_BASE, &s->vdisk_ram);
		dinfo->is_default = 1;
		rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
		} else {
		fprintf(stderr, "qemu: could not load ram disk '%s'\n",
		blk_bs(blk)->filename);
		exit(1);
		}
		}
		serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
		serial_hds[0], DEVICE_BIG_ENDIAN);

		empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
		sun4v_rtc_init(NIAGARA_RTC_BASE);
		}

		static void niagara_class_init(ObjectClass oc, void data)
		{
		MachineClass *mc = MACHINE_CLASS(oc);

		mc->desc = "Sun4v platform, Niagara";
		mc->init = niagara_init;
		mc->max_cpus = 1; /* XXX for now */
		mc->default_boot_order = "c";
		}

		static const TypeInfo niagara_type = {
		.name = MACHINE_TYPE_NAME("niagara"),
		.parent = TYPE_MACHINE,
		.class_init = niagara_class_init,
		};

		static void niagara_register_types(void)
		{
		type_register_static(&niagara_type);
		}

		type_init(niagara_register_types)

hw/sparc64/sparc64.c

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Original line number	Diff line number	Diff line
		/*
		* QEMU Sun4u/Sun4v System Emulator common routines
		*
		* Copyright (c) 2005 Fabrice Bellard
		*
		* Permission is hereby granted, free of charge, to any person obtaining a copy
		* of this software and associated documentation files (the "Software"), to deal
		* in the Software without restriction, including without limitation the rights
		* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
		* copies of the Software, and to permit persons to whom the Software is
		* furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
		* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
		* THE SOFTWARE.
		*/


		#include "qemu/osdep.h"
		#include "cpu.h"
		#include "hw/char/serial.h"
		#include "hw/sparc/sparc64.h"
		#include "qemu/timer.h"


		//#define DEBUG_IRQ
		//#define DEBUG_TIMER

		#ifdef DEBUG_IRQ
		#define CPUIRQ_DPRINTF(fmt, ...) \
		do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
		#else
		#define CPUIRQ_DPRINTF(fmt, ...)
		#endif

		#ifdef DEBUG_TIMER
		#define TIMER_DPRINTF(fmt, ...) \
		do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
		#else
		#define TIMER_DPRINTF(fmt, ...)
		#endif

		#define TICK_MAX 0x7fffffffffffffffULL

		void cpu_check_irqs(CPUSPARCState *env)
		{
		CPUState *cs;
		uint32_t pil = env->pil_in \|
		(env->softint & ~(SOFTINT_TIMER \| SOFTINT_STIMER));

		/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
		if (env->ivec_status & 0x20) {
		return;
		}
		cs = CPU(sparc_env_get_cpu(env));
		/* check if TM or SM in SOFTINT are set
		setting these also causes interrupt 14 */
		if (env->softint & (SOFTINT_TIMER \| SOFTINT_STIMER)) {
		pil \|= 1 << 14;
		}

		/* The bit corresponding to psrpil is (1<< psrpil), the next bit
		is (2 << psrpil). */
		if (pil < (2 << env->psrpil)) {
		if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
		CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
		env->interrupt_index);
		env->interrupt_index = 0;
		cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
		}
		return;
		}

		if (cpu_interrupts_enabled(env)) {

		unsigned int i;

		for (i = 15; i > env->psrpil; i--) {
		if (pil & (1 << i)) {
		int old_interrupt = env->interrupt_index;
		int new_interrupt = TT_EXTINT \| i;

		if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
		&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
		CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
		"current %x >= pending %x\n",
		env->tl, cpu_tsptr(env)->tt, new_interrupt);
		} else if (old_interrupt != new_interrupt) {
		env->interrupt_index = new_interrupt;
		CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
		old_interrupt, new_interrupt);
		cpu_interrupt(cs, CPU_INTERRUPT_HARD);
		}
		break;
		}
		}
		} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
		CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
		"current interrupt %x\n",
		pil, env->pil_in, env->softint, env->interrupt_index);
		env->interrupt_index = 0;
		cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
		}
		}

		static void cpu_kick_irq(SPARCCPU *cpu)
		{
		CPUState *cs = CPU(cpu);
		CPUSPARCState *env = &cpu->env;

		cs->halted = 0;
		cpu_check_irqs(env);
		qemu_cpu_kick(cs);
		}

		void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level)
		{
		SPARCCPU *cpu = opaque;
		CPUSPARCState *env = &cpu->env;
		CPUState *cs;

		if (level) {
		if (!(env->ivec_status & 0x20)) {
		CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
		cs = CPU(cpu);
		cs->halted = 0;
		env->interrupt_index = TT_IVEC;
		env->ivec_status \|= 0x20;
		env->ivec_data[0] = (0x1f << 6) \| irq;
		env->ivec_data[1] = 0;
		env->ivec_data[2] = 0;
		cpu_interrupt(cs, CPU_INTERRUPT_HARD);
		}
		} else {
		if (env->ivec_status & 0x20) {
		CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
		cs = CPU(cpu);
		env->ivec_status &= ~0x20;
		cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
		}
		}
		}

		typedef struct ResetData {
		SPARCCPU *cpu;
		uint64_t prom_addr;
		} ResetData;

		static CPUTimer cpu_timer_create(const char name, SPARCCPU *cpu,
		QEMUBHFunc *cb, uint32_t frequency,
		uint64_t disabled_mask, uint64_t npt_mask)
		{
		CPUTimer *timer = g_malloc0(sizeof(CPUTimer));

		timer->name = name;
		timer->frequency = frequency;
		timer->disabled_mask = disabled_mask;
		timer->npt_mask = npt_mask;

		timer->disabled = 1;
		timer->npt = 1;
		timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

		timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);

		return timer;
		}

		static void cpu_timer_reset(CPUTimer *timer)
		{
		timer->disabled = 1;
		timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

		timer_del(timer->qtimer);
		}

		static void main_cpu_reset(void *opaque)
		{
		ResetData s = (ResetData )opaque;
		CPUSPARCState *env = &s->cpu->env;
		static unsigned int nr_resets;

		cpu_reset(CPU(s->cpu));

		cpu_timer_reset(env->tick);
		cpu_timer_reset(env->stick);
		cpu_timer_reset(env->hstick);

		env->gregs[1] = 0; /* Memory start */
		env->gregs[2] = ram_size; /* Memory size */
		env->gregs[3] = 0; /* Machine description XXX */
		if (nr_resets++ == 0) {
		/* Power on reset */
		env->pc = s->prom_addr + 0x20ULL;
		} else {
		env->pc = s->prom_addr + 0x40ULL;
		}
		env->npc = env->pc + 4;
		}

		static void tick_irq(void *opaque)
		{
		SPARCCPU *cpu = opaque;
		CPUSPARCState *env = &cpu->env;

		CPUTimer *timer = env->tick;

		if (timer->disabled) {
		CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
		return;
		} else {
		CPUIRQ_DPRINTF("tick: fire\n");
		}

		env->softint \|= SOFTINT_TIMER;
		cpu_kick_irq(cpu);
		}

		static void stick_irq(void *opaque)
		{
		SPARCCPU *cpu = opaque;
		CPUSPARCState *env = &cpu->env;

		CPUTimer *timer = env->stick;

		if (timer->disabled) {
		CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
		return;
		} else {
		CPUIRQ_DPRINTF("stick: fire\n");
		}

		env->softint \|= SOFTINT_STIMER;
		cpu_kick_irq(cpu);
		}

		static void hstick_irq(void *opaque)
		{
		SPARCCPU *cpu = opaque;
		CPUSPARCState *env = &cpu->env;

		CPUTimer *timer = env->hstick;

		if (timer->disabled) {
		CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
		return;
		} else {
		CPUIRQ_DPRINTF("hstick: fire\n");
		}

		env->softint \|= SOFTINT_STIMER;
		cpu_kick_irq(cpu);
		}

		static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
		{
		return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
		}

		static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
		{
		return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
		}

		void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
		{
		uint64_t real_count = count & ~timer->npt_mask;
		uint64_t npt_bit = count & timer->npt_mask;

		int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
		cpu_to_timer_ticks(real_count, timer->frequency);

		TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
		timer->name, real_count,
		timer->npt ? "disabled" : "enabled", timer);

		timer->npt = npt_bit ? 1 : 0;
		timer->clock_offset = vm_clock_offset;
		}

		uint64_t cpu_tick_get_count(CPUTimer *timer)
		{
		uint64_t real_count = timer_to_cpu_ticks(
		qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
		timer->frequency);

		TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
		timer->name, real_count,
		timer->npt ? "disabled" : "enabled", timer);

		if (timer->npt) {
		real_count \|= timer->npt_mask;
		}

		return real_count;
		}

		void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
		{
		int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

		uint64_t real_limit = limit & ~timer->disabled_mask;
		timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;

		int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
		timer->clock_offset;

		if (expires < now) {
		expires = now + 1;
		}

		TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
		"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
		timer->name, real_limit,
		timer->disabled ? "disabled" : "enabled",
		timer, limit,
		timer_to_cpu_ticks(now - timer->clock_offset,
		timer->frequency),
		timer_to_cpu_ticks(expires - now, timer->frequency));

		if (!real_limit) {
		TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
		timer->name);
		timer_del(timer->qtimer);
		} else if (timer->disabled) {
		timer_del(timer->qtimer);
		} else {
		timer_mod(timer->qtimer, expires);
		}
		}

		SPARCCPU sparc64_cpu_devinit(const char cpu_model,
		const char *default_cpu_model, uint64_t prom_addr)
		{
		SPARCCPU *cpu;
		CPUSPARCState *env;
		ResetData *reset_info;

		uint32_t tick_frequency = 100 * 1000000;
		uint32_t stick_frequency = 100 * 1000000;
		uint32_t hstick_frequency = 100 * 1000000;

		if (cpu_model == NULL) {
		cpu_model = default_cpu_model;
		}
		cpu = cpu_sparc_init(cpu_model);
		if (cpu == NULL) {
		fprintf(stderr, "Unable to find Sparc CPU definition\n");
		exit(1);
		}
		env = &cpu->env;

		env->tick = cpu_timer_create("tick", cpu, tick_irq,
		tick_frequency, TICK_INT_DIS,
		TICK_NPT_MASK);

		env->stick = cpu_timer_create("stick", cpu, stick_irq,
		stick_frequency, TICK_INT_DIS,
		TICK_NPT_MASK);

		env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
		hstick_frequency, TICK_INT_DIS,
		TICK_NPT_MASK);

		reset_info = g_malloc0(sizeof(ResetData));
		reset_info->cpu = cpu;
		reset_info->prom_addr = prom_addr;
		qemu_register_reset(main_cpu_reset, reset_info);

		return cpu;
		}