Commit 0f589782 authored by Francisco Iglesias's avatar Francisco Iglesias Committed by Peter Maydell
Browse files

m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) 



Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.

Signed-off-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
Acked-by: default avatarMarcin Krzemiński <mar.krzeminski@gmail.com>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20171126231634.9531-4-frasse.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent a87fc364

hw/block/m25p80.c

+7 −0
Original line number Diff line number Diff line
@@ -331,7 +331,10 @@ typedef enum { 
    WRDI = 0x4,

    RDSR = 0x5,

    WREN = 0x6,

    BRRD = 0x16,

    BRWR = 0x17,

    JEDEC_READ = 0x9f,

    BULK_ERASE_60 = 0x60,

    BULK_ERASE = 0xc7,

    READ_FSR = 0x70,

    RDCR = 0x15,
@@ -704,6 +707,7 @@ static void complete_collecting_data(Flash *s) 
            s->write_enable = false;

        }

        break;

    case BRWR:

    case EXTEND_ADDR_WRITE:

        s->ear = s->data[0];

        break;
@@ -1050,6 +1054,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) 
        s->state = STATE_READING_DATA;

        break;



    case BULK_ERASE_60:

    case BULK_ERASE:

        if (s->write_enable) {

            DB_PRINT_L(0, "chip erase\n");
@@ -1067,12 +1072,14 @@ static void decode_new_cmd(Flash *s, uint32_t value) 
    case EX_4BYTE_ADDR:

        s->four_bytes_address_mode = false;

        break;

    case BRRD:

    case EXTEND_ADDR_READ:

        s->data[0] = s->ear;

        s->pos = 0;

        s->len = 1;

        s->state = STATE_READING_DATA;

        break;

    case BRWR:

    case EXTEND_ADDR_WRITE:

        if (s->write_enable) {

            s->needed_bytes = 1;