Commit 0e12e61f authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20150610-1' into staging 



stdvga: factor out mmio subregion init
virtio-gpu: add virtio gpu core code, 2d mode

# gpg: Signature made Wed Jun 10 10:03:11 2015 BST using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"

* remotes/kraxel/tags/pull-vga-20150610-1:
  virtio-gpu/2d: add virtio gpu core code
  virtio: update headers, add virtio-gpu (2d)
  stdvga: factor out mmio subregion init
  stdvga: pass VGACommonState instead of PCIVGAState
  stdvga: fix offset in pci_vga_ioport_read

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 3974c9d8 62232bf4

hw/display/Makefile.objs

+2 −0
Original line number Diff line number Diff line
@@ -34,3 +34,5 @@ obj-$(CONFIG_CG3) += cg3.o 
obj-$(CONFIG_VGA) += vga.o



common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o



obj-$(CONFIG_VIRTIO) += virtio-gpu.o

hw/display/vga-pci.c

+49 −48
Original line number Diff line number Diff line
@@ -54,9 +54,7 @@ typedef struct PCIVGAState { 
    VGACommonState vga;

    uint32_t flags;

    MemoryRegion mmio;

    MemoryRegion ioport;

    MemoryRegion bochs;

    MemoryRegion qext;

    MemoryRegion mrs[3];

} PCIVGAState;



#define TYPE_PCI_VGA "pci-vga"
@@ -76,16 +74,16 @@ static const VMStateDescription vmstate_vga_pci = { 
static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,

                                    unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;

    uint64_t ret = 0;



    switch (size) {

    case 1:

        ret = vga_ioport_read(&d->vga, addr);

        ret = vga_ioport_read(s, addr + 0x3c0);

        break;

    case 2:

        ret  = vga_ioport_read(&d->vga, addr);

        ret |= vga_ioport_read(&d->vga, addr+1) << 8;

        ret  = vga_ioport_read(s, addr + 0x3c0);

        ret |= vga_ioport_read(s, addr + 0x3c1) << 8;

        break;

    }

    return ret;
@@ -94,11 +92,11 @@ static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr, 
static void pci_vga_ioport_write(void *ptr, hwaddr addr,

                                 uint64_t val, unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;



    switch (size) {

    case 1:

        vga_ioport_write(&d->vga, addr + 0x3c0, val);

        vga_ioport_write(s, addr + 0x3c0, val);

        break;

    case 2:

        /*
@@ -106,8 +104,8 @@ static void pci_vga_ioport_write(void *ptr, hwaddr addr, 
         * indexed registers with a single word write because the

         * index byte is updated first.

         */

        vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);

        vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);

        vga_ioport_write(s, addr + 0x3c0, val & 0xff);

        vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);

        break;

    }

}
@@ -125,21 +123,21 @@ static const MemoryRegionOps pci_vga_ioport_ops = { 
static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,

                                   unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;

    int index = addr >> 1;



    vbe_ioport_write_index(&d->vga, 0, index);

    return vbe_ioport_read_data(&d->vga, 0);

    vbe_ioport_write_index(s, 0, index);

    return vbe_ioport_read_data(s, 0);

}



static void pci_vga_bochs_write(void *ptr, hwaddr addr,

                                uint64_t val, unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;

    int index = addr >> 1;



    vbe_ioport_write_index(&d->vga, 0, index);

    vbe_ioport_write_data(&d->vga, 0, val);

    vbe_ioport_write_index(s, 0, index);

    vbe_ioport_write_data(s, 0, val);

}



static const MemoryRegionOps pci_vga_bochs_ops = {
@@ -154,13 +152,13 @@ static const MemoryRegionOps pci_vga_bochs_ops = { 


static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;



    switch (addr) {

    case PCI_VGA_QEXT_REG_SIZE:

        return PCI_VGA_QEXT_SIZE;

    case PCI_VGA_QEXT_REG_BYTEORDER:

        return d->vga.big_endian_fb ?

        return s->big_endian_fb ?

            PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;

    default:

        return 0;
@@ -170,15 +168,15 @@ static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) 
static void pci_vga_qext_write(void *ptr, hwaddr addr,

                               uint64_t val, unsigned size)

{

    PCIVGAState *d = ptr;

    VGACommonState *s = ptr;



    switch (addr) {

    case PCI_VGA_QEXT_REG_BYTEORDER:

        if (val == PCI_VGA_QEXT_BIG_ENDIAN) {

            d->vga.big_endian_fb = true;

            s->big_endian_fb = true;

        }

        if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {

            d->vga.big_endian_fb = false;

            s->big_endian_fb = false;

        }

        break;

    }
@@ -206,10 +204,34 @@ static const MemoryRegionOps pci_vga_qext_ops = { 
    .endianness = DEVICE_LITTLE_ENDIAN,

};



static void pci_std_vga_mmio_region_init(VGACommonState *s,

                                         MemoryRegion *parent,

                                         MemoryRegion *subs,

                                         bool qext)

{

    memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,

                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);

    memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,

                                &subs[0]);



    memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,

                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);

    memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,

                                &subs[1]);



    if (qext) {

        memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,

                              "qemu extended regs", PCI_VGA_QEXT_SIZE);

        memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,

                                    &subs[2]);

    }

}



static void pci_std_vga_realize(PCIDevice *dev, Error **errp)

{

    PCIVGAState *d = PCI_VGA(dev);

    VGACommonState *s = &d->vga;

    bool qext = false;



    /* vga + console init */

    vga_common_init(s, OBJECT(dev), true);
@@ -224,23 +246,12 @@ static void pci_std_vga_realize(PCIDevice *dev, Error **errp) 
    /* mmio bar for vga register access */

    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {

        memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);

        memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,

                              "vga ioports remapped", PCI_VGA_IOPORT_SIZE);

        memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,

                              "bochs dispi interface", PCI_VGA_BOCHS_SIZE);



        memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,

                                    &d->ioport);

        memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,

                                    &d->bochs);



        if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {

            memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,

                                  "qemu extended regs", PCI_VGA_QEXT_SIZE);

            memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,

                                        &d->qext);

            qext = true;

            pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);

        }

        pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);



        pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);

    }
@@ -262,6 +273,7 @@ static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 
{

    PCIVGAState *d = PCI_VGA(dev);

    VGACommonState *s = &d->vga;

    bool qext = false;



    /* vga + console init */

    vga_common_init(s, OBJECT(dev), false);
@@ -269,23 +281,12 @@ static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp) 


    /* mmio bar */

    memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);

    memory_region_init_io(&d->ioport, OBJECT(dev), &pci_vga_ioport_ops, d,

                          "vga ioports remapped", PCI_VGA_IOPORT_SIZE);

    memory_region_init_io(&d->bochs, OBJECT(dev), &pci_vga_bochs_ops, d,

                          "bochs dispi interface", PCI_VGA_BOCHS_SIZE);



    memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,

                                &d->ioport);

    memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,

                                &d->bochs);



    if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {

        memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,

                              "qemu extended regs", PCI_VGA_QEXT_SIZE);

        memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,

                                    &d->qext);

        qext = true;

        pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);

    }

    pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);



    pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);

    pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);

hw/display/virtio-gpu.c

0 → 100644
+918 −0

File added.

Preview size limit exceeded, changes collapsed.

include/hw/virtio/virtio-gpu.h

0 → 100644
+145 −0
Original line number Diff line number Diff line 
/*

 * Virtio GPU Device

 *

 * Copyright Red Hat, Inc. 2013-2014

 *

 * Authors:

 *     Dave Airlie <airlied@redhat.com>

 *     Gerd Hoffmann <kraxel@redhat.com>

 *

 * This work is licensed under the terms of the GNU GPL, version 2.

 * See the COPYING file in the top-level directory.

 */



#ifndef _QEMU_VIRTIO_VGA_H

#define _QEMU_VIRTIO_VGA_H



#include "qemu/queue.h"

#include "ui/qemu-pixman.h"

#include "ui/console.h"

#include "hw/virtio/virtio.h"

#include "hw/pci/pci.h"



#include "standard-headers/linux/virtio_gpu.h"

#define TYPE_VIRTIO_GPU "virtio-gpu-device"

#define VIRTIO_GPU(obj)                                        \

        OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)



#define VIRTIO_ID_GPU 16



#define VIRTIO_GPU_MAX_SCANOUT 4



struct virtio_gpu_simple_resource {

    uint32_t resource_id;

    uint32_t width;

    uint32_t height;

    uint32_t format;

    struct iovec *iov;

    unsigned int iov_cnt;

    uint32_t scanout_bitmask;

    pixman_image_t *image;

    QTAILQ_ENTRY(virtio_gpu_simple_resource) next;

};



struct virtio_gpu_scanout {

    QemuConsole *con;

    DisplaySurface *ds;

    uint32_t width, height;

    int x, y;

    int invalidate;

    uint32_t resource_id;

    QEMUCursor *current_cursor;

};



struct virtio_gpu_requested_state {

    uint32_t width, height;

    int x, y;

};



struct virtio_gpu_conf {

    uint32_t max_outputs;

};



struct virtio_gpu_ctrl_command {

    VirtQueueElement elem;

    VirtQueue *vq;

    struct virtio_gpu_ctrl_hdr cmd_hdr;

    uint32_t error;

    bool finished;

    QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;

};



typedef struct VirtIOGPU {

    VirtIODevice parent_obj;



    QEMUBH *ctrl_bh;

    QEMUBH *cursor_bh;

    VirtQueue *ctrl_vq;

    VirtQueue *cursor_vq;



    int enable;



    int config_size;

    DeviceState *qdev;



    QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;

    QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;



    struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUT];

    struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUT];



    struct virtio_gpu_conf conf;

    int enabled_output_bitmask;

    struct virtio_gpu_config virtio_config;



    QEMUTimer *fence_poll;

    QEMUTimer *print_stats;



    struct {

        uint32_t inflight;

        uint32_t max_inflight;

        uint32_t requests;

        uint32_t req_3d;

        uint32_t bytes_3d;

    } stats;

} VirtIOGPU;



extern const GraphicHwOps virtio_gpu_ops;



/* to share between PCI and VGA */

#define DEFINE_VIRTIO_GPU_PCI_PROPERTIES(_state)               \

    DEFINE_PROP_BIT("ioeventfd", _state, flags,                \

                    VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, false), \

    DEFINE_PROP_UINT32("vectors", _state, nvectors, 3)



#define DEFINE_VIRTIO_GPU_PROPERTIES(_state, _conf_field)               \

    DEFINE_PROP_UINT32("max_outputs", _state, _conf_field.max_outputs, 1)



#define VIRTIO_GPU_FILL_CMD(out) do {                                   \

        size_t s;                                                       \

        s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0,          \

                       &out, sizeof(out));                              \

        if (s != sizeof(out)) {                                         \

            qemu_log_mask(LOG_GUEST_ERROR,                              \

                          "%s: command size incorrect %zu vs %zu\n",    \

                          __func__, s, sizeof(out));                    \

            return;                                                     \

        }                                                               \

    } while (0)



/* virtio-gpu.c */

void virtio_gpu_ctrl_response(VirtIOGPU *g,

                              struct virtio_gpu_ctrl_command *cmd,

                              struct virtio_gpu_ctrl_hdr *resp,

                              size_t resp_len);

void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,

                                     struct virtio_gpu_ctrl_command *cmd,

                                     enum virtio_gpu_ctrl_type type);

void virtio_gpu_get_display_info(VirtIOGPU *g,

                                 struct virtio_gpu_ctrl_command *cmd);

int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,

                                  struct virtio_gpu_ctrl_command *cmd,

                                  struct iovec **iov);

void virtio_gpu_cleanup_mapping_iov(struct iovec *iov, uint32_t count);



#endif

include/standard-headers/linux/virtio_gpu.h

0 → 100644
+204 −0
Original line number Diff line number Diff line 
/*

 * Virtio GPU Device

 *

 * Copyright Red Hat, Inc. 2013-2014

 *

 * Authors:

 *     Dave Airlie <airlied@redhat.com>

 *     Gerd Hoffmann <kraxel@redhat.com>

 *

 * This header is BSD licensed so anyone can use the definitions

 * to implement compatible drivers/servers:

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 * 3. Neither the name of IBM nor the names of its contributors

 *    may be used to endorse or promote products derived from this software

 *    without specific prior written permission.

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF

 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT

 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF

 * SUCH DAMAGE.

 */



#ifndef VIRTIO_GPU_HW_H

#define VIRTIO_GPU_HW_H



enum virtio_gpu_ctrl_type {

	VIRTIO_GPU_UNDEFINED = 0,



	/* 2d commands */

	VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,

	VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,

	VIRTIO_GPU_CMD_RESOURCE_UNREF,

	VIRTIO_GPU_CMD_SET_SCANOUT,

	VIRTIO_GPU_CMD_RESOURCE_FLUSH,

	VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,

	VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,

	VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,



	/* cursor commands */

	VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,

	VIRTIO_GPU_CMD_MOVE_CURSOR,



	/* success responses */

	VIRTIO_GPU_RESP_OK_NODATA = 0x1100,

	VIRTIO_GPU_RESP_OK_DISPLAY_INFO,



	/* error responses */

	VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,

	VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,

	VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,

	VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,

	VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,

	VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,

};



#define VIRTIO_GPU_FLAG_FENCE (1 << 0)



struct virtio_gpu_ctrl_hdr {

	uint32_t type;

	uint32_t flags;

	uint64_t fence_id;

	uint32_t ctx_id;

	uint32_t padding;

};



/* data passed in the cursor vq */



struct virtio_gpu_cursor_pos {

	uint32_t scanout_id;

	uint32_t x;

	uint32_t y;

	uint32_t padding;

};



/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */

struct virtio_gpu_update_cursor {

	struct virtio_gpu_ctrl_hdr hdr;

	struct virtio_gpu_cursor_pos pos;  /* update & move */

	uint32_t resource_id;           /* update only */

	uint32_t hot_x;                 /* update only */

	uint32_t hot_y;                 /* update only */

	uint32_t padding;

};



/* data passed in the control vq, 2d related */



struct virtio_gpu_rect {

	uint32_t x;

	uint32_t y;

	uint32_t width;

	uint32_t height;

};



/* VIRTIO_GPU_CMD_RESOURCE_UNREF */

struct virtio_gpu_resource_unref {

	struct virtio_gpu_ctrl_hdr hdr;

	uint32_t resource_id;

	uint32_t padding;

};



/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */

struct virtio_gpu_resource_create_2d {

	struct virtio_gpu_ctrl_hdr hdr;

	uint32_t resource_id;

	uint32_t format;

	uint32_t width;

	uint32_t height;

};



/* VIRTIO_GPU_CMD_SET_SCANOUT */

struct virtio_gpu_set_scanout {

	struct virtio_gpu_ctrl_hdr hdr;

	struct virtio_gpu_rect r;

	uint32_t scanout_id;

	uint32_t resource_id;

};



/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */

struct virtio_gpu_resource_flush {

	struct virtio_gpu_ctrl_hdr hdr;

	struct virtio_gpu_rect r;

	uint32_t resource_id;

	uint32_t padding;

};



/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */

struct virtio_gpu_transfer_to_host_2d {

	struct virtio_gpu_ctrl_hdr hdr;

	struct virtio_gpu_rect r;

	uint64_t offset;

	uint32_t resource_id;

	uint32_t padding;

};



struct virtio_gpu_mem_entry {

	uint64_t addr;

	uint32_t length;

	uint32_t padding;

};



/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */

struct virtio_gpu_resource_attach_backing {

	struct virtio_gpu_ctrl_hdr hdr;

	uint32_t resource_id;

	uint32_t nr_entries;

};



/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */

struct virtio_gpu_resource_detach_backing {

	struct virtio_gpu_ctrl_hdr hdr;

	uint32_t resource_id;

	uint32_t padding;

};



/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */

#define VIRTIO_GPU_MAX_SCANOUTS 16

struct virtio_gpu_resp_display_info {

	struct virtio_gpu_ctrl_hdr hdr;

	struct virtio_gpu_display_one {

		struct virtio_gpu_rect r;

		uint32_t enabled;

		uint32_t flags;

	} pmodes[VIRTIO_GPU_MAX_SCANOUTS];

};



#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)



struct virtio_gpu_config {

	uint32_t events_read;

	uint32_t events_clear;

	uint32_t num_scanouts;

	uint32_t reserved;

};



/* simple formats for fbcon/X use */

enum virtio_gpu_formats {

	VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,

	VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,

	VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,

	VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,



	VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,

	VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,



	VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,

	VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,

};



#endif