Commit 0e0456ab authored Aug 24, 2018 by Peter Maydell

target/arm: Implement RAZ/WI HACTLR2



The v8 AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2.
We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI.
(We put the regdef next to ACTLR_EL2 as a reminder in case we
ever make ACTLR_EL2 something other than RAZ/WI).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180820153020.21478-2-peter.maydell@linaro.org

parent cac0d808

target/arm/helper.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -5459,6 +5459,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
		REGINFO_SENTINEL
		};
		define_arm_cp_regs(cpu, auxcr_reginfo);
		if (arm_feature(env, ARM_FEATURE_V8)) {
		/* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */
		ARMCPRegInfo hactlr2_reginfo = {
		.name = "HACTLR2", .state = ARM_CP_STATE_AA32,
		.cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
		.access = PL2_RW, .type = ARM_CP_CONST,
		.resetvalue = 0
		};
		define_one_arm_cp_reg(cpu, &hactlr2_reginfo);
		}
		}

		if (arm_feature(env, ARM_FEATURE_CBAR)) {