Commit 0dc62847 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190715' into staging 



target-arm queue:
 * report ARMv8-A FP support for AArch32 -cpu max
 * hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
 * hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
 * hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
 * hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
 * hw/arm/virt: Fix non-secure flash mode
 * pl031: Correctly migrate state when using -rtc clock=host
 * fix regression that meant arm926 and arm1026 lost VFP
   double-precision support
 * v8M: NS BusFault on vector table fetch escalates to NS HardFault

# gpg: Signature made Mon 15 Jul 2019 14:41:25 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190715:
  target/arm: NS BusFault on vector table fetch escalates to NS HardFault
  target/arm: Set VFP-related MVFR0 fields for arm926 and arm1026
  pl031: Correctly migrate state when using -rtc clock=host
  hw/arm/virt: Fix non-secure flash mode
  hw/display/xlnx_dp: Avoid crash when reading empty RX FIFO
  hw/ssi/mss-spi: Avoid crash when reading empty RX FIFO
  hw/ssi/xilinx_spips: Avoid out-of-bound access to lqspi_buf[]
  hw/ssi/xilinx_spips: Avoid AXI writes to the LQSPI linear memory
  hw/ssi/xilinx_spips: Convert lqspi_read() to read_with_attrs
  target/arm: report ARMv8-A FP support for AArch32 -cpu max

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents b9404bf5 51c9122e

hw/arm/virt.c

+1 −1
Original line number Diff line number Diff line
@@ -1674,7 +1674,7 @@ static void machvirt_init(MachineState *machine) 
                                    &machine->device_memory->mr);

    }



    virt_flash_fdt(vms, sysmem, secure_sysmem);

    virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);



    create_gic(vms, pic);

hw/core/machine.c

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ GlobalProperty hw_compat_4_0[] = { 
    { "virtio-gpu-pci", "edid", "false" },

    { "virtio-device", "use-started", "false" },

    { "virtio-balloon-device", "qemu-4-0-config-size", "true" },

    { "pl031", "migrate-tick-offset", "false" },

};

const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);

hw/display/xlnx_dp.c

+11 −4
Original line number Diff line number Diff line
@@ -427,11 +427,18 @@ static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s) 
    uint8_t ret;



    if (fifo8_is_empty(&s->rx_fifo)) {

        DPRINTF("rx_fifo underflow..\n");

        abort();

    }

        qemu_log_mask(LOG_GUEST_ERROR,

                      "%s: Reading empty RX_FIFO\n",

                      __func__);

        /*

         * The datasheet is not clear about the reset value, it seems

         * to be unspecified. We choose to return '0'.

         */

        ret = 0;

    } else {

        ret = fifo8_pop(&s->rx_fifo);

        DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);

    }

    return ret;

}

hw/ssi/mss-spi.c

+7 −1
Original line number Diff line number Diff line
@@ -165,7 +165,13 @@ spi_read(void *opaque, hwaddr addr, unsigned int size) 
    case R_SPI_RX:

        s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;

        s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;

        if (fifo32_is_empty(&s->rx_fifo)) {

            qemu_log_mask(LOG_GUEST_ERROR,

                          "%s: Reading empty RX_FIFO\n",

                          __func__);

        } else {

            ret = fifo32_pop(&s->rx_fifo);

        }

        if (fifo32_is_empty(&s->rx_fifo)) {

            s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;

        }

hw/ssi/xilinx_spips.c

+31 −12
Original line number Diff line number Diff line
@@ -1202,28 +1202,47 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) 
    }

}



static uint64_t

lqspi_read(void *opaque, hwaddr addr, unsigned int size)

static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,

                              unsigned size, MemTxAttrs attrs)

{

    XilinxQSPIPS *q = opaque;

    uint32_t ret;

    XilinxQSPIPS *q = XILINX_QSPIPS(opaque);



    if (addr >= q->lqspi_cached_addr &&

            addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {

        uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];

        ret = cpu_to_le32(*(uint32_t *)retp);

        DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,

                   (unsigned)ret);

        return ret;

    } else {

        *value = cpu_to_le32(*(uint32_t *)retp);

        DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",

                   addr, *value);

        return MEMTX_OK;

    }



    lqspi_load_cache(opaque, addr);

        return lqspi_read(opaque, addr, size);

    return lqspi_read(opaque, addr, value, size, attrs);

}



static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,

                               unsigned size, MemTxAttrs attrs)

{

    /*

     * From UG1085, Chapter 24 (Quad-SPI controllers):

     * - Writes are ignored

     * - AXI writes generate an external AXI slave error (SLVERR)

     */

    qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64

                                   " (value: 0x%" PRIx64 "\n",

                  __func__, size << 3, offset, value);



    return MEMTX_ERROR;

}



static const MemoryRegionOps lqspi_ops = {

    .read = lqspi_read,

    .read_with_attrs = lqspi_read,

    .write_with_attrs = lqspi_write,

    .endianness = DEVICE_NATIVE_ENDIAN,

    .impl = {

        .min_access_size = 4,

        .max_access_size = 4,

    },

    .valid = {

        .min_access_size = 1,

        .max_access_size = 4