Commit 0da0fb06 authored by Jingqi Liu's avatar Jingqi Liu Committed by Eduardo Habkost
Browse files

x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature 

The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other cores in the same coherence domain,
especially if the line was written by the core that demotes the line.

Intel Snow Ridge has added new cpu feature, CLDEMOTE.
The new cpu feature needs to be exposed to guest VM.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\


architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: default avatarJingqi Liu <jingqi.liu@intel.com>
Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com>
Reviewed-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent a1849515

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -494,7 +494,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,

            "la57", NULL, NULL, NULL,

            NULL, NULL, "rdpid", NULL,

            NULL, NULL, NULL, NULL,

            NULL, "cldemote", NULL, NULL,

            NULL, NULL, NULL, NULL,

        },

        .cpuid_eax = 7,

target/i386/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -680,6 +680,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */

#define CPUID_7_0_ECX_LA57     (1U << 16)

#define CPUID_7_0_ECX_RDPID    (1U << 22)

#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */



#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */