Commit 0ca540db authored by Peter Maydell's avatar Peter Maydell
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' into staging 



target-arm queue:
 * implement WFE as yield (improves performance with emulated SMP)
 * fixes to avoid undefined behaviour shifting left into sign bit
 * libvixl format string fixes for 32 bit hosts
 * fix build error when intptr_t and tcg_target_long are different
   sizes (eg x32)
 * implement PMCCNTR register
 * fix incorrect setting of E bit in CPSR (broke booting under
   KVM on ARM)

# gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140310:
  target-arm: Implement WFE as a yield operation
  hw/arm/musicpal: Avoid shifting left into sign bit
  hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit
  hw/arm/omap1.c: Avoid shifting left into sign bit
  pxa2xx: Don't shift into sign bit
  libvixl: Fix format strings for several int64_t values
  target-arm: Fix intptr_t vs tcg_target_long
  target-arm: Implements the ARM PMCCNTR register
  target-arm: Fix incorrect setting of E bit in CPSR

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents ed9b103d 72c1d3af

disas/libvixl/a64/disasm-a64.cc

+10 −10
Original line number Diff line number Diff line
@@ -1342,7 +1342,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
        ASSERT(format[5] == 'L');

        AppendToOutput("#0x%" PRIx64, instr->ImmMoveWide());

        if (instr->ShiftMoveWide() > 0) {

          AppendToOutput(", lsl #%d", 16 * instr->ShiftMoveWide());

          AppendToOutput(", lsl #%" PRId64, 16 * instr->ShiftMoveWide());

        }

      }

      return 8;
@@ -1391,7 +1391,7 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
    }

    case 'F': {  // IFPSingle, IFPDouble or IFPFBits.

      if (format[3] == 'F') {  // IFPFbits.

        AppendToOutput("#%d", 64 - instr->FPScale());

        AppendToOutput("#%" PRId64, 64 - instr->FPScale());

        return 8;

      } else {

        AppendToOutput("#0x%" PRIx64 " (%.4f)", instr->ImmFP(),
@@ -1412,23 +1412,23 @@ int Disassembler::SubstituteImmediateField(Instruction* instr, 
      return 5;

    }

    case 'P': {  // IP - Conditional compare.

      AppendToOutput("#%d", instr->ImmCondCmp());

      AppendToOutput("#%" PRId64, instr->ImmCondCmp());

      return 2;

    }

    case 'B': {  // Bitfields.

      return SubstituteBitfieldImmediateField(instr, format);

    }

    case 'E': {  // IExtract.

      AppendToOutput("#%d", instr->ImmS());

      AppendToOutput("#%" PRId64, instr->ImmS());

      return 8;

    }

    case 'S': {  // IS - Test and branch bit.

      AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |

      AppendToOutput("#%" PRId64, (instr->ImmTestBranchBit5() << 5) |

                                  instr->ImmTestBranchBit40());

      return 2;

    }

    case 'D': {  // IDebug - HLT and BRK instructions.

      AppendToOutput("#0x%x", instr->ImmException());

      AppendToOutput("#0x%" PRIx64, instr->ImmException());

      return 6;

    }

    default: {
@@ -1598,12 +1598,12 @@ int Disassembler::SubstituteExtendField(Instruction* instr, 
      (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) ||

       (instr->ExtendMode() == UXTX))) {

    if (instr->ImmExtendShift() > 0) {

      AppendToOutput(", lsl #%d", instr->ImmExtendShift());

      AppendToOutput(", lsl #%" PRId64, instr->ImmExtendShift());

    }

  } else {

    AppendToOutput(", %s", extend_mode[instr->ExtendMode()]);

    if (instr->ImmExtendShift() > 0) {

      AppendToOutput(" #%d", instr->ImmExtendShift());

      AppendToOutput(" #%" PRId64, instr->ImmExtendShift());

    }

  }

  return 3;
@@ -1632,7 +1632,7 @@ int Disassembler::SubstituteLSRegOffsetField(Instruction* instr, 
  if (!((ext == UXTX) && (shift == 0))) {

    AppendToOutput(", %s", extend_mode[ext]);

    if (shift != 0) {

      AppendToOutput(" #%d", instr->SizeLS());

      AppendToOutput(" #%" PRId64, instr->SizeLS());

    }

  }

  return 9;

hw/arm/musicpal.c

+2 −2
Original line number Diff line number Diff line
@@ -110,10 +110,10 @@ 
#define MP_PHY_88E3015          0x01410E20



/* TX descriptor status */

#define MP_ETH_TX_OWN           (1 << 31)

#define MP_ETH_TX_OWN           (1U << 31)



/* RX descriptor status */

#define MP_ETH_RX_OWN           (1 << 31)

#define MP_ETH_RX_OWN           (1U << 31)



/* Interrupt cause/mask bits */

#define MP_ETH_IRQ_RX_BIT       0

hw/arm/omap1.c

+14 −10
Original line number Diff line number Diff line
@@ -809,22 +809,26 @@ static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, 
                uint32_t diff, uint32_t value)

{

    if (s->compat1509) {

        if (diff & (1 << 31))			/* MCBSP3_CLK_HIZ_DI */

            omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),

                            (value >> 31) & 1);

        if (diff & (1 << 1))			/* CLK32K */

            omap_clk_onoff(omap_findclk(s, "clk32k_out"),

                            (~value >> 1) & 1);

        if (diff & (1U << 31)) {

            /* MCBSP3_CLK_HIZ_DI */

            omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), (value >> 31) & 1);

        }

        if (diff & (1 << 1)) {

            /* CLK32K */

            omap_clk_onoff(omap_findclk(s, "clk32k_out"), (~value >> 1) & 1);

        }

    }

}



static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,

                uint32_t diff, uint32_t value)

{

    if (diff & (1 << 31))			/* CONF_MOD_UART3_CLK_MODE_R */

    if (diff & (1U << 31)) {

        /* CONF_MOD_UART3_CLK_MODE_R */

        omap_clk_reparent(omap_findclk(s, "uart3_ck"),

                          omap_findclk(s, ((value >> 31) & 1) ?

                                       "ck_48m" : "armper_ck"));

    }

    if (diff & (1 << 30))			/* CONF_MOD_UART2_CLK_MODE_R */

         omap_clk_reparent(omap_findclk(s, "uart2_ck"),

                         omap_findclk(s, ((value >> 30) & 1) ?

hw/arm/pxa2xx.c

+3 −3
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, 


    case 1:

        /* Idle */

        if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */

        if (!(s->cm_regs[CCCR >> 2] & (1U << 31))) { /* CPDIS */

            cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);

            break;

        }
@@ -496,7 +496,7 @@ typedef struct { 
#define SSCR0_SSE	(1 << 7)

#define SSCR0_RIM	(1 << 22)

#define SSCR0_TIM	(1 << 23)

#define SSCR0_MOD	(1 << 31)

#define SSCR0_MOD       (1U << 31)

#define SSCR0_DSS(x)	(((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)

#define SSCR1_RIE	(1 << 0)

#define SSCR1_TIE	(1 << 1)
@@ -1006,7 +1006,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr, 


    switch (addr) {

    case RTTR:

        if (!(s->rttr & (1 << 31))) {

        if (!(s->rttr & (1U << 31))) {

            pxa2xx_rtc_hzupdate(s);

            s->rttr = value;

            pxa2xx_rtc_alarm_update(s, s->rtsr);

hw/arm/pxa2xx_gpio.c

+1 −1
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ static void pxa2xx_gpio_set(void *opaque, int line, int level) 
    }



    bank = line >> 5;

    mask = 1 << (line & 31);

    mask = 1U << (line & 31);



    if (level) {

        s->status[bank] |= s->rising[bank] & mask &