Commit 0c9c3a9e authored by Andrzej Zaborowski's avatar Andrzej Zaborowski
Browse files

arm: Don't potentially overwrite input registers in add2, sub2. 

According to malc TCG will often genereate an add2/sub2/mul2 with low
half of the output in the same register as high half of one of the
inputs, so account for that.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
parent 63d41246

tcg/arm/tcg-target.c

+13 −4
Original line number Diff line number Diff line
@@ -295,11 +295,20 @@ static inline void tcg_out_dat_reg2(TCGContext *s, 
                int cond, int opc0, int opc1, int rd0, int rd1,

                int rn0, int rn1, int rm0, int rm1, int shift)

{

    if (rd0 == rn1 || rd0 == rm1) {

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |

                        (rn0 << 16) | (8 << 12) | shift | rm0);

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |

                        (rn1 << 16) | (rd1 << 12) | shift | rm1);

        tcg_out_dat_reg(s, cond, ARITH_MOV,

                        rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));

    } else {

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |

                        (rn0 << 16) | (rd0 << 12) | shift | rm0);

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |

                        (rn1 << 16) | (rd1 << 12) | shift | rm1);

    }

}



static inline void tcg_out_dat_imm(TCGContext *s,

                int cond, int opc, int rd, int rn, int im)