Commit 0c7a8b9b authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 



pc, acpi, pci, virtio: fixes, cleanups, features, tests

Some fixes and cleanups. New tests.
Configurable tx queue size for virtio-net.

Signed-off-by: default avatarMichael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Mon 03 Jul 2017 20:43:17 BST
# gpg:                using RSA key 0x281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream: (21 commits)
  i386/acpi: update expected acpi files
  virtio-net: fix tx queue size for !vhost-user
  tests: Add unit tests for the VM Generation ID feature
  vhost-user: unregister slave req handler at cleanup time
  vhost: ensure vhost_ops are set before calling iotlb callback
  intel_iommu: fix migration breakage on mr switch
  hw/acpi: remove dead acpi code
  fw_cfg: move setting of FW_CFG_VERSION_DMA bit to fw_cfg_init1()
  fw_cfg: don't map the fw_cfg IO ports in fw_cfg_io_realize()
  i386/kvm/pci-assign: Use errp directly rather than local_err
  i386/kvm/pci-assign: Fix return type of verify_irqchip_kernel()
  pci: Convert shpc_init() to Error
  pci: Convert to realize
  pci: Replace pci_add_capability2() with pci_add_capability()
  pci: Make errp the last parameter of pci_add_capability()
  pci: Fix the wrong assertion.
  pci: Add comment for pci_add_capability2()
  pci: Clean up error checking in pci_add_capability()
  intel_iommu: relax iq tail check on VTD_GCMD_QIE enable
  hw/pci-bridge/dec: Classify the DEC PCI bridge as bridge device
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents fd479c60 d2f9ca94

hw/i386/acpi-build.c

+0 −10
Original line number Diff line number Diff line
@@ -1912,16 +1912,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, 
        build_piix4_pci_hotplug(dsdt);

        build_piix4_pci0_int(dsdt);

    } else {

        sb_scope = aml_scope("_SB");

        aml_append(sb_scope,

            aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));

        aml_append(sb_scope,

            aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));

        field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);

        aml_append(field, aml_named_field("PCIB", 8));

        aml_append(sb_scope, field);

        aml_append(dsdt, sb_scope);



        sb_scope = aml_scope("_SB");

        dev = aml_device("PCI0");

        aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));

hw/i386/amd_iommu.c

+17 −7
Original line number Diff line number Diff line
@@ -1158,13 +1158,23 @@ static void amdvi_realize(DeviceState *dev, Error **err) 
    x86_iommu->type = TYPE_AMD;

    qdev_set_parent_bus(DEVICE(&s->pci), &bus->qbus);

    object_property_set_bool(OBJECT(&s->pci), true, "realized", err);

    s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,

                                         AMDVI_CAPAB_SIZE);

    assert(s->capab_offset > 0);

    ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE);

    assert(ret > 0);

    ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE);

    assert(ret > 0);

    ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0,

                                         AMDVI_CAPAB_SIZE, err);

    if (ret < 0) {

        return;

    }

    s->capab_offset = ret;



    ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0,

                             AMDVI_CAPAB_REG_SIZE, err);

    if (ret < 0) {

        return;

    }

    ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0,

                             AMDVI_CAPAB_REG_SIZE, err);

    if (ret < 0) {

        return;

    }



    /* set up MMIO */

    memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",

hw/i386/intel_iommu.c

+34 −14
Original line number Diff line number Diff line
@@ -1450,10 +1450,7 @@ static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val) 
    return iaig;

}



static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)

{

    return s->iq_tail == 0;

}

static void vtd_fetch_inv_desc(IntelIOMMUState *s);



static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)

{
@@ -1468,7 +1465,6 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) 
    trace_vtd_inv_qi_enable(en);



    if (en) {

        if (vtd_queued_inv_enable_check(s)) {

        s->iq = iqa_val & VTD_IQA_IQA_MASK;

        /* 2^(x+8) entries */

        s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
@@ -1476,8 +1472,17 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en) 
        trace_vtd_inv_qi_setup(s->iq, s->iq_size);

        /* Ok - report back to driver */

        vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);

        } else {

            trace_vtd_err_qi_enable(s->iq_tail);



        if (s->iq_tail != 0) {

            /*

             * This is a spec violation but Windows guests are known to set up

             * Queued Invalidation this way so we allow the write and process

             * Invalidation Descriptors right away.

             */

            trace_vtd_warn_invalid_qi_tail(s->iq_tail);

            if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {

                vtd_fetch_inv_desc(s);

            }

        }

    } else {

        if (vtd_queued_inv_disable_check(s)) {
@@ -2332,11 +2337,26 @@ static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu, 
    }

}



static int vtd_post_load(void *opaque, int version_id)

{

    IntelIOMMUState *iommu = opaque;



    /*

     * Memory regions are dynamically turned on/off depending on

     * context entry configurations from the guest. After migration,

     * we need to make sure the memory regions are still correct.

     */

    vtd_switch_address_space_all(iommu);



    return 0;

}



static const VMStateDescription vtd_vmstate = {

    .name = "iommu-intel",

    .version_id = 1,

    .minimum_version_id = 1,

    .priority = MIG_PRI_IOMMU,

    .post_load = vtd_post_load,

    .fields = (VMStateField[]) {

        VMSTATE_UINT64(root, IntelIOMMUState),

        VMSTATE_UINT64(intr_root, IntelIOMMUState),

hw/i386/kvm/pci-assign.c

+20 −34
Original line number Diff line number Diff line
@@ -824,12 +824,13 @@ static void assign_device(AssignedDevice *dev, Error **errp) 
    }

}



static void verify_irqchip_in_kernel(Error **errp)

static int verify_irqchip_in_kernel(Error **errp)

{

    if (kvm_irqchip_in_kernel()) {

        return;

        return -1;

    }

    error_setg(errp, "pci-assign requires KVM with in-kernel irqchip enabled");

    return 0;

}



static int assign_intx(AssignedDevice *dev, Error **errp)
@@ -838,7 +839,6 @@ static int assign_intx(AssignedDevice *dev, Error **errp) 
    PCIINTxRoute intx_route;

    bool intx_host_msi;

    int r;

    Error *local_err = NULL;



    /* Interrupt PIN 0 means don't use INTx */

    if (assigned_dev_pci_read_byte(&dev->dev, PCI_INTERRUPT_PIN) == 0) {
@@ -846,9 +846,7 @@ static int assign_intx(AssignedDevice *dev, Error **errp) 
        return 0;

    }



    verify_irqchip_in_kernel(&local_err);

    if (local_err) {

        error_propagate(errp, local_err);

    if (verify_irqchip_in_kernel(errp) < 0) {

        return -ENOTSUP;

    }
@@ -1234,7 +1232,6 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
    AssignedDevice *dev = PCI_ASSIGN(pci_dev);

    PCIRegion *pci_region = dev->real_device.regions;

    int ret, pos;

    Error *local_err = NULL;



    /* Clear initial capabilities pointer and status copied from hw */

    pci_set_byte(pci_dev->config + PCI_CAPABILITY_LIST, 0);
@@ -1246,18 +1243,15 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
     * MSI capability is the 1st capability in capability config */

    pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI, 0);

    if (pos != 0 && kvm_check_extension(kvm_state, KVM_CAP_ASSIGN_DEV_IRQ)) {

        verify_irqchip_in_kernel(&local_err);

        if (local_err) {

            error_propagate(errp, local_err);

        if (verify_irqchip_in_kernel(errp) < 0) {

            return -ENOTSUP;

        }

        dev->dev.cap_present |= QEMU_PCI_CAP_MSI;

        dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI;

        /* Only 32-bit/no-mask currently supported */

        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_MSI, pos, 10,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSI, pos, 10,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }

        pci_dev->msi_cap = pos;
@@ -1281,17 +1275,14 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
        uint32_t msix_table_entry;

        uint16_t msix_max;



        verify_irqchip_in_kernel(&local_err);

        if (local_err) {

            error_propagate(errp, local_err);

        if (verify_irqchip_in_kernel(errp) < 0) {

            return -ENOTSUP;

        }

        dev->dev.cap_present |= QEMU_PCI_CAP_MSIX;

        dev->cap.available |= ASSIGNED_DEVICE_CAP_MSIX;

        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_MSIX, pos, 12,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, pos, 12,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }

        pci_dev->msix_cap = pos;
@@ -1318,10 +1309,9 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
    if (pos) {

        uint16_t pmc;



        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SIZEOF,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SIZEOF,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }
@@ -1386,10 +1376,9 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
            return -EINVAL;

        }



        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_EXP, pos, size,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_EXP, pos, size,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }
@@ -1462,10 +1451,9 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
        uint32_t status;



        /* Only expose the minimum, 8 byte capability */

        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_PCIX, pos, 8,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_PCIX, pos, 8,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }
@@ -1490,10 +1478,9 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
    pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VPD, 0);

    if (pos) {

        /* Direct R/W passthrough */

        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_VPD, pos, 8,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_VPD, pos, 8,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }
@@ -1508,10 +1495,9 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp) 
        pos += PCI_CAP_LIST_NEXT) {

        uint8_t len = pci_get_byte(pci_dev->config + pos + PCI_CAP_FLAGS);

        /* Direct R/W passthrough */

        ret = pci_add_capability2(pci_dev, PCI_CAP_ID_VNDR, pos, len,

                                  &local_err);

        ret = pci_add_capability(pci_dev, PCI_CAP_ID_VNDR, pos, len,

                                  errp);

        if (ret < 0) {

            error_propagate(errp, local_err);

            return ret;

        }

hw/i386/trace-events

+1 −1
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ vtd_err_dmar_slpte_read_error(uint64_t iova, int level) "iova 0x%"PRIx64" level 
vtd_err_dmar_slpte_perm_error(uint64_t iova, int level, uint64_t slpte, bool is_write) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64" write %d"

vtd_err_dmar_slpte_resv_error(uint64_t iova, int level, uint64_t slpte) "iova 0x%"PRIx64" level %d slpte 0x%"PRIx64

vtd_err_dmar_translate(uint8_t bus, uint8_t slot, uint8_t func, uint64_t iova) "dev %02x:%02x.%02x iova 0x%"PRIx64

vtd_err_qi_enable(uint16_t tail) "tail 0x%"PRIx16

vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16

vtd_err_qi_disable(uint16_t head, uint16_t tail, int type) "head 0x%"PRIx16" tail 0x%"PRIx16" last_desc_type %d"

vtd_err_qi_tail(uint16_t tail, uint16_t size) "tail 0x%"PRIx16" size 0x%"PRIx16

vtd_err_irte(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64