Commit 0c575703 authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

spapr/xive: add hcall support when under KVM 



XIVE hcalls are all redirected to QEMU as none are on a fast path.
When necessary, QEMU invokes KVM through specific ioctls to perform
host operations. QEMU should have done the necessary checks before
calling KVM and, in case of failure, H_HARDWARE is simply returned.

H_INT_ESB is a special case that could have been handled under KVM
but the impact on performance was low when under QEMU. Here are some
figures :

    kernel irqchip      OFF          ON
    H_INT_ESB                    KVM   QEMU

    rtl8139 (LSI )      1.19     1.24  1.23  Gbits/sec
    virtio             31.80    42.30   --   Gbits/sec

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Message-Id: <20190513084245.25755-4-clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 38afd772

hw/intc/spapr_xive.c

+82 −8
Original line number Diff line number Diff line
@@ -86,6 +86,22 @@ static int spapr_xive_target_to_nvt(uint32_t target, 
 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8

 * priorities per CPU

 */

int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,

                             uint32_t *out_server, uint8_t *out_prio)

{



    assert(end_blk == SPAPR_XIVE_BLOCK_ID);



    if (out_server) {

        *out_server = end_idx >> 3;

    }



    if (out_prio) {

        *out_prio = end_idx & 0x7;

    }

    return 0;

}



static void spapr_xive_cpu_to_end(PowerPCCPU *cpu, uint8_t prio,

                                  uint8_t *out_end_blk, uint32_t *out_end_idx)

{
@@ -792,6 +808,16 @@ static target_ulong h_int_set_source_config(PowerPCCPU *cpu, 
        new_eas.w = xive_set_field64(EAS_END_DATA, new_eas.w, eisn);

    }



    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        kvmppc_xive_set_source_config(xive, lisn, &new_eas, &local_err);

        if (local_err) {

            error_report_err(local_err);

            return H_HARDWARE;

        }

    }



out:

    xive->eat[lisn] = new_eas;

    return H_SUCCESS;
@@ -1103,6 +1129,16 @@ static target_ulong h_int_set_queue_config(PowerPCCPU *cpu, 
     */



out:

    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        kvmppc_xive_set_queue_config(xive, end_blk, end_idx, &end, &local_err);

        if (local_err) {

            error_report_err(local_err);

            return H_HARDWARE;

        }

    }



    /* Update END */

    memcpy(&xive->endt[end_idx], &end, sizeof(XiveEND));

    return H_SUCCESS;
@@ -1194,6 +1230,16 @@ static target_ulong h_int_get_queue_config(PowerPCCPU *cpu, 
        args[2] = 0;

    }



    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        kvmppc_xive_get_queue_config(xive, end_blk, end_idx, end, &local_err);

        if (local_err) {

            error_report_err(local_err);

            return H_HARDWARE;

        }

    }



    /* TODO: do we need any locking on the END ? */

    if (flags & SPAPR_XIVE_END_DEBUG) {

        /* Load the event queue generation number into the return flags */
@@ -1346,6 +1392,10 @@ static target_ulong h_int_esb(PowerPCCPU *cpu, 
        return H_P3;

    }



    if (kvm_irqchip_in_kernel()) {

        args[0] = kvmppc_xive_esb_rw(xsrc, lisn, offset, data,

                                     flags & SPAPR_XIVE_ESB_STORE);

    } else {

        mmio_addr = xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + offset;



        if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8,
@@ -1355,6 +1405,7 @@ static target_ulong h_int_esb(PowerPCCPU *cpu, 
            return H_HARDWARE;

        }

        args[0] = (flags & SPAPR_XIVE_ESB_STORE) ? -1 : data;

    }

    return H_SUCCESS;

}
@@ -1411,7 +1462,20 @@ static target_ulong h_int_sync(PowerPCCPU *cpu, 
     * This is not needed when running the emulation under QEMU

     */



    /* This is not real hardware. Nothing to be done */

    /*

     * This is not real hardware. Nothing to be done unless when

     * under KVM

     */



    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        kvmppc_xive_sync_source(xive, lisn, &local_err);

        if (local_err) {

            error_report_err(local_err);

            return H_HARDWARE;

        }

    }

    return H_SUCCESS;

}
@@ -1446,6 +1510,16 @@ static target_ulong h_int_reset(PowerPCCPU *cpu, 
    }



    device_reset(DEVICE(xive));



    if (kvm_irqchip_in_kernel()) {

        Error *local_err = NULL;



        kvmppc_xive_reset(xive, &local_err);

        if (local_err) {

            error_report_err(local_err);

            return H_HARDWARE;

        }

    }

    return H_SUCCESS;

}

hw/intc/spapr_xive_kvm.c

+197 −0
Original line number Diff line number Diff line
@@ -89,6 +89,50 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) 
 * XIVE Interrupt Source (KVM)

 */



void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,

                                   Error **errp)

{

    uint32_t end_idx;

    uint32_t end_blk;

    uint8_t priority;

    uint32_t server;

    bool masked;

    uint32_t eisn;

    uint64_t kvm_src;

    Error *local_err = NULL;



    assert(xive_eas_is_valid(eas));



    end_idx = xive_get_field64(EAS_END_INDEX, eas->w);

    end_blk = xive_get_field64(EAS_END_BLOCK, eas->w);

    eisn = xive_get_field64(EAS_END_DATA, eas->w);

    masked = xive_eas_is_masked(eas);



    spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);



    kvm_src = priority << KVM_XIVE_SOURCE_PRIORITY_SHIFT &

        KVM_XIVE_SOURCE_PRIORITY_MASK;

    kvm_src |= server << KVM_XIVE_SOURCE_SERVER_SHIFT &

        KVM_XIVE_SOURCE_SERVER_MASK;

    kvm_src |= ((uint64_t) masked << KVM_XIVE_SOURCE_MASKED_SHIFT) &

        KVM_XIVE_SOURCE_MASKED_MASK;

    kvm_src |= ((uint64_t)eisn << KVM_XIVE_SOURCE_EISN_SHIFT) &

        KVM_XIVE_SOURCE_EISN_MASK;



    kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_SOURCE_CONFIG, lisn,

                      &kvm_src, true, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }

}



void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp)

{

    kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_SOURCE_SYNC, lisn,

                      NULL, true, errp);

}



/*

 * At reset, the interrupt sources are simply created and MASKED. We

 * only need to inform the KVM XIVE device about their type: LSI or
@@ -125,6 +169,64 @@ void kvmppc_xive_source_reset(XiveSource *xsrc, Error **errp) 
    }

}



/*

 * This is used to perform the magic loads on the ESB pages, described

 * in xive.h.

 *

 * Memory barriers should not be needed for loads (no store for now).

 */

static uint64_t xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,

                            uint64_t data, bool write)

{

    uint64_t *addr = xsrc->esb_mmap + xive_source_esb_mgmt(xsrc, srcno) +

        offset;



    if (write) {

        *addr = cpu_to_be64(data);

        return -1;

    } else {

        /* Prevent the compiler from optimizing away the load */

        volatile uint64_t value = be64_to_cpu(*addr);

        return value;

    }

}



static uint8_t xive_esb_read(XiveSource *xsrc, int srcno, uint32_t offset)

{

    return xive_esb_rw(xsrc, srcno, offset, 0, 0) & 0x3;

}



static void xive_esb_trigger(XiveSource *xsrc, int srcno)

{

    uint64_t *addr = xsrc->esb_mmap + xive_source_esb_page(xsrc, srcno);



    *addr = 0x0;

}



uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,

                            uint64_t data, bool write)

{

    if (write) {

        return xive_esb_rw(xsrc, srcno, offset, data, 1);

    }



    /*

     * Special Load EOI handling for LSI sources. Q bit is never set

     * and the interrupt should be re-triggered if the level is still

     * asserted.

     */

    if (xive_source_irq_is_lsi(xsrc, srcno) &&

        offset == XIVE_ESB_LOAD_EOI) {

        xive_esb_read(xsrc, srcno, XIVE_ESB_SET_PQ_00);

        if (xsrc->status[srcno] & XIVE_STATUS_ASSERTED) {

            xive_esb_trigger(xsrc, srcno);

        }

        return 0;

    } else {

        return xive_esb_rw(xsrc, srcno, offset, 0, 0);

    }

}



void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val)

{

    XiveSource *xsrc = opaque;
@@ -155,6 +257,101 @@ void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val) 
/*

 * sPAPR XIVE interrupt controller (KVM)

 */

void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,

                                  uint32_t end_idx, XiveEND *end,

                                  Error **errp)

{

    struct kvm_ppc_xive_eq kvm_eq = { 0 };

    uint64_t kvm_eq_idx;

    uint8_t priority;

    uint32_t server;

    Error *local_err = NULL;



    assert(xive_end_is_valid(end));



    /* Encode the tuple (server, prio) as a KVM EQ index */

    spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);



    kvm_eq_idx = priority << KVM_XIVE_EQ_PRIORITY_SHIFT &

            KVM_XIVE_EQ_PRIORITY_MASK;

    kvm_eq_idx |= server << KVM_XIVE_EQ_SERVER_SHIFT &

        KVM_XIVE_EQ_SERVER_MASK;



    kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_EQ_CONFIG, kvm_eq_idx,

                      &kvm_eq, false, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }



    /*

     * The EQ index and toggle bit are updated by HW. These are the

     * only fields from KVM we want to update QEMU with. The other END

     * fields should already be in the QEMU END table.

     */

    end->w1 = xive_set_field32(END_W1_GENERATION, 0ul, kvm_eq.qtoggle) |

        xive_set_field32(END_W1_PAGE_OFF, 0ul, kvm_eq.qindex);

}



void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,

                                  uint32_t end_idx, XiveEND *end,

                                  Error **errp)

{

    struct kvm_ppc_xive_eq kvm_eq = { 0 };

    uint64_t kvm_eq_idx;

    uint8_t priority;

    uint32_t server;

    Error *local_err = NULL;



    /*

     * Build the KVM state from the local END structure.

     */



    kvm_eq.flags = 0;

    if (xive_get_field32(END_W0_UCOND_NOTIFY, end->w0)) {

        kvm_eq.flags |= KVM_XIVE_EQ_ALWAYS_NOTIFY;

    }



    /*

     * If the hcall is disabling the EQ, set the size and page address

     * to zero. When migrating, only valid ENDs are taken into

     * account.

     */

    if (xive_end_is_valid(end)) {

        kvm_eq.qshift = xive_get_field32(END_W0_QSIZE, end->w0) + 12;

        kvm_eq.qaddr  = xive_end_qaddr(end);

        /*

         * The EQ toggle bit and index should only be relevant when

         * restoring the EQ state

         */

        kvm_eq.qtoggle = xive_get_field32(END_W1_GENERATION, end->w1);

        kvm_eq.qindex  = xive_get_field32(END_W1_PAGE_OFF, end->w1);

    } else {

        kvm_eq.qshift = 0;

        kvm_eq.qaddr  = 0;

    }



    /* Encode the tuple (server, prio) as a KVM EQ index */

    spapr_xive_end_to_target(end_blk, end_idx, &server, &priority);



    kvm_eq_idx = priority << KVM_XIVE_EQ_PRIORITY_SHIFT &

            KVM_XIVE_EQ_PRIORITY_MASK;

    kvm_eq_idx |= server << KVM_XIVE_EQ_SERVER_SHIFT &

        KVM_XIVE_EQ_SERVER_MASK;



    kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_EQ_CONFIG, kvm_eq_idx,

                      &kvm_eq, true, &local_err);

    if (local_err) {

        error_propagate(errp, local_err);

        return;

    }

}



void kvmppc_xive_reset(SpaprXive *xive, Error **errp)

{

    kvm_device_access(xive->fd, KVM_DEV_XIVE_GRP_CTRL, KVM_DEV_XIVE_RESET,

                      NULL, true, errp);

}



static void *kvmppc_xive_mmap(SpaprXive *xive, int pgoff, size_t len,

                              Error **errp)

include/hw/ppc/spapr_xive.h

+15 −0
Original line number Diff line number Diff line
@@ -55,9 +55,24 @@ void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); 
void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);

void spapr_xive_map_mmio(SpaprXive *xive);



int spapr_xive_end_to_target(uint8_t end_blk, uint32_t end_idx,

                             uint32_t *out_server, uint8_t *out_prio);



/*

 * KVM XIVE device helpers

 */

void kvmppc_xive_connect(SpaprXive *xive, Error **errp);

void kvmppc_xive_reset(SpaprXive *xive, Error **errp);

void kvmppc_xive_set_source_config(SpaprXive *xive, uint32_t lisn, XiveEAS *eas,

                                   Error **errp);

void kvmppc_xive_sync_source(SpaprXive *xive, uint32_t lisn, Error **errp);

uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno, uint32_t offset,

                            uint64_t data, bool write);

void kvmppc_xive_set_queue_config(SpaprXive *xive, uint8_t end_blk,

                                 uint32_t end_idx, XiveEND *end,

                                 Error **errp);

void kvmppc_xive_get_queue_config(SpaprXive *xive, uint8_t end_blk,

                                 uint32_t end_idx, XiveEND *end,

                                 Error **errp);



#endif /* PPC_SPAPR_XIVE_H */