Commit 0c28d0d0 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging 



- Many fixes from the floor as usual
- New "edu" device (v1->v2: fix 32-bit compilation)
- Disabling HLE and RTM on Haswell & Broadwell
- kvm_stat updates
- Added --enable-modules to Travis, in preparation for switching
  the default

# gpg: Signature made Mon 26 Jan 2015 11:44:40 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  kvm_stat: Add RESET support for perf event ioctl
  target-i386: Disable HLE and RTM on Haswell & Broadwell
  sparse: Fix build with sparse on .S files
  exec: fix madvise of NULL pointer
  .travis.yml: Add "--enable-modules"
  apic: do not dereference pointer before it is checked for NULL
  kvm_stat: Print errno when syscall to perf_event_open() fails
  kvm_stat: Update exit reasons to the latest defintion
  kvm_stat: Add aarch64 support
  hw: misc, add educational driver
  vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR*
  qemu-timer: introduce timer_deinit
  qemu-timer: add timer_init and timer_init_ns/us/ms
  target-i386: make xmm_regs 512-bit wide
  target-i386: use vmstate_offset_sub_array for AVX registers
  tests/multiboot: Add test for modules
  multiboot: Fix offset of bootloader name
  tests/multiboot: Update reference output
  pc: fix KVM features in pc-1.3 and earlier machine types

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d109f80a fc116efa

.travis.yml

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@@ -98,3 +98,6 @@ matrix: 
          EXTRA_PKGS="liblttng-ust-dev liburcu-dev"

          EXTRA_CONFIG="--enable-trace-backends=ust"

      compiler: gcc

    - env: TARGETS=i386-softmmu,x86_64-softmmu

           EXTRA_CONFIG="--enable-modules"

      compiler: gcc

MAINTAINERS

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@@ -599,6 +599,11 @@ F: hw/net/opencores_eth.c 


Devices

-------

EDU

M: Jiri Slaby <jslaby@suse.cz>

S: Maintained

F: hw/misc/edu.c



IDE

M: Kevin Wolf <kwolf@redhat.com>

M: Stefan Hajnoczi <stefanha@redhat.com>

configure

+1 −0
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@@ -4938,6 +4938,7 @@ echo "QEMU_CFLAGS=$QEMU_CFLAGS" >> $config_host_mak 
echo "QEMU_INCLUDES=$QEMU_INCLUDES" >> $config_host_mak

if test "$sparse" = "yes" ; then

  echo "CC           := REAL_CC=\"\$(CC)\" cgcc"       >> $config_host_mak

  echo "CPP          := REAL_CC=\"\$(CPP)\" cgcc"      >> $config_host_mak

  echo "CXX          := REAL_CC=\"\$(CXX)\" cgcc"      >> $config_host_mak

  echo "HOST_CC      := REAL_CC=\"\$(HOST_CC)\" cgcc"  >> $config_host_mak

  echo "QEMU_CFLAGS  += -Wbitwise -Wno-transparent-union -Wno-old-initializer -Wno-non-pointer-null" >> $config_host_mak

default-configs/pci.mak

+1 −0
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@@ -32,3 +32,4 @@ CONFIG_PCI_TESTDEV=y 
CONFIG_NVME_PCI=y

CONFIG_SD=y

CONFIG_SDHCI=y

CONFIG_EDU=y

docs/specs/edu.txt

0 → 100644
+110 −0
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EDU device

==========



Copyright (c) 2014-2015 Jiri Slaby



This document is licensed under the GPLv2 (or later).



This is an educational device for writing (kernel) drivers. Its original

intention was to support the Linux kernel lectures taught at the Masaryk

University. Students are given this virtual device and are expected to write a

driver with I/Os, IRQs, DMAs and such.



The devices behaves very similar to the PCI bridge present in the COMBO6 cards

developed under the Liberouter wings. Both PCI device ID and PCI space is

inherited from that device.



Command line switches:

    -device edu[,dma_mask=mask]



    dma_mask makes the virtual device work with DMA addresses with the given

    mask. For educational purposes, the device supports only 28 bits (256 MiB)

    by default. Students shall set dma_mask for the device in the OS driver

    properly.



PCI specs

---------



PCI ID: 1234:11e8



PCI Region 0:

   I/O memory, 1 MB in size. Users are supposed to communicate with the card

   through this memory.



MMIO area spec

--------------



Only size == 4 accesses are allowed for addresses < 0x80. size == 4 or

size == 8 for the rest.



0x00 (RO) : identification (0xRRrr00edu)

	    RR -- major version

	    rr -- minor version



0x04 (RW) : card liveness check

	    It is a simple value inversion (~ C operator).



0x08 (RW) : factorial computation

	    The stored value is taken and factorial of it is put back here.

	    This happens only after factorial bit in the status register (0x20

	    below) is cleared.



0x20 (RW) : status register, bitwise OR

	    0x01 -- computing factorial (RO)

	    0x80 -- raise interrupt 0x01 after finishing factorial computation



0x24 (RO) : interrupt status register

	    It contains values which raised the interrupt (see interrupt raise

	    register below).



0x60 (WO) : interrupt raise register

	    Raise an interrupt. The value will be put to the interrupt status

	    register (using bitwise OR).



0x64 (WO) : interrupt acknowledge register

	    Clear an interrupt. The value will be cleared from the interrupt

	    status register. This needs to be done from the ISR to stop

	    generating interrupts.



0x80 (RW) : DMA source address

	    Where to perform the DMA from.



0x88 (RW) : DMA destination address

	    Where to perform the DMA to.



0x90 (RW) : DMA transfer count

	    The size of the area to perform the DMA on.



0x98 (RW) : DMA command register, bitwise OR

	    0x01 -- start transfer

	    0x02 -- direction (0: from RAM to EDU, 1: from EDU to RAM)

	    0x04 -- raise interrupt 0x100 after finishing the DMA



IRQ controller

--------------

An IRQ is generated when written to the interrupt raise register. The value

appears in interrupt status register when the interrupt is raised and has to

be written to the interrupt acknowledge register to lower it.



DMA controller

--------------

One has to specify, source, destination, size, and start the transfer. One

4096 bytes long buffer at offset 0x40000 is available in the EDU device. I.e.

one can perform DMA to/from this space when programmed properly.



Example of transferring a 100 byte block to and from the buffer using a given

PCI address 'addr':

addr     -> DMA source address

0x40000  -> DMA destination address

100      -> DMA transfer count

1        -> DMA command register

while (DMA command register & 1)

	;



0x40000  -> DMA source address

addr+100 -> DMA destination address

100      -> DMA transfer count

3        -> DMA command register

while (DMA command register & 1)

	;