Commit 0b62159b authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Adjust FPCR_MASK for FZ16 



When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.

Fixes: d81ce0ef
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180810193129.1556-2-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ebe31c0a

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -1269,7 +1269,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); 
 * we store the underlying state in fpscr and just mask on read/write.

 */

#define FPSR_MASK 0xf800009f

#define FPCR_MASK 0x07f79f00

#define FPCR_MASK 0x07ff9f00



#define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */

#define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */

target/arm/helper.c

+5 −0
Original line number Diff line number Diff line
@@ -11349,6 +11349,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 
    int i;

    uint32_t changed;



    /* When ARMv8.2-FP16 is not supported, FZ16 is RES0.  */

    if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {

        val &= ~FPCR_FZ16;

    }



    changed = env->vfp.xregs[ARM_VFP_FPSCR];

    env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);

    env->vfp.vec_len = (val >> 16) & 7;