Commit 0b591184 authored by Stefan Markovic's avatar Stefan Markovic Committed by Aleksandar Markovic
Browse files

target/mips: Add emulation of DSP ASE for nanoMIPS - part 6 



Add emulation of DSP ASE instructions for nanoMIPS - part 6.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarStefan Markovic <smarkovic@wavecomp.com>
parent 4c75c985

target/mips/translate.c

+58 −0
Original line number Diff line number Diff line
@@ -17912,6 +17912,60 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, 
    tcg_temp_free(t0);

}









static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,









                                          int rt, int rs, int rd)









{









    TCGv t0 = tcg_temp_new();









    TCGv rs_t = tcg_temp_new();

















    gen_load_gpr(rs_t, rs);

















    switch (opc) {









    case NM_SHRA_R_QB:









        check_dspr2(ctx);









        tcg_gen_movi_tl(t0, rd >> 2);









        switch (extract32(ctx->opcode, 12, 1)) {









        case 0:









            /* NM_SHRA_QB */









            gen_helper_shra_qb(t0, t0, rs_t);









            gen_store_gpr(t0, rt);









            break;









        case 1:









            /* NM_SHRA_R_QB */









            gen_helper_shra_r_qb(t0, t0, rs_t);









            gen_store_gpr(t0, rt);









            break;









        }









        break;









    case NM_SHRL_PH:









        check_dspr2(ctx);









        tcg_gen_movi_tl(t0, rd >> 1);









        gen_helper_shrl_ph(t0, t0, rs_t);









        gen_store_gpr(t0, rt);









        break;









    case NM_REPL_QB:









        check_dsp(ctx);









        {









            int16_t imm;









            target_long result;









            imm = extract32(ctx->opcode, 13, 8);









            result = (uint32_t)imm << 24 |









                     (uint32_t)imm << 16 |









                     (uint32_t)imm << 8  |









                     (uint32_t)imm;









            result = (int32_t)result;









            tcg_gen_movi_tl(t0, result);









            gen_store_gpr(t0, rt);









        }









        break;









    default:









        generate_exception_end(ctx, EXCP_RI);









        break;









    }









    tcg_temp_free(t0);









    tcg_temp_free(rs_t);









}

























static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)









{








@@ -18007,6 +18061,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)







        }









        break;









    case NM_POOL32AXF_7:









        {









            int32_t op1 = extract32(ctx->opcode, 9, 3);









            gen_pool32axf_7_nanomips_insn(ctx, op1, rt, rs, rd);









        }









        break;









    default:









        generate_exception_end(ctx, EXCP_RI);