Commit 0b45451e authored by Peter Maydell's avatar Peter Maydell
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target-arm: Implement AArch64 dummy breakpoint and watchpoint registers 



In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
parent e60cef86

target-arm/cpu.h

+4 −0
Original line number Diff line number Diff line
@@ -216,6 +216,10 @@ typedef struct CPUARMState { 
        uint32_t c15_diagnostic; /* diagnostic register */

        uint32_t c15_power_diagnostic;

        uint32_t c15_power_control; /* power control */

        uint64_t dbgbvr[16]; /* breakpoint value registers */

        uint64_t dbgbcr[16]; /* breakpoint control registers */

        uint64_t dbgwvr[16]; /* watchpoint value registers */

        uint64_t dbgwcr[16]; /* watchpoint control registers */

    } cp15;



    struct {

target-arm/helper.c

+32 −0
Original line number Diff line number Diff line
@@ -1761,6 +1761,37 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) 
    return CP_ACCESS_OK;

}



static void define_aarch64_debug_regs(ARMCPU *cpu)

{

    /* Define breakpoint and watchpoint registers. These do nothing

     * but read as written, for now.

     */

    int i;



    for (i = 0; i < 16; i++) {

        ARMCPRegInfo dbgregs[] = {

            { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,

              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,

              .access = PL1_RW,

              .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },

            { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,

              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,

              .access = PL1_RW,

              .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },

            { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,

              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,

              .access = PL1_RW,

              .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },

            { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,

              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,

              .access = PL1_RW,

              .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },

               REGINFO_SENTINEL

        };

        define_arm_cp_regs(cpu, dbgregs);

    }

}



void register_cp_regs_for_features(ARMCPU *cpu)

{

    /* Register all the coprocessor registers based on feature bits */
@@ -1902,6 +1933,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
        };

        define_arm_cp_regs(cpu, v8_idregs);

        define_arm_cp_regs(cpu, v8_cp_reginfo);

        define_aarch64_debug_regs(cpu);

    }

    if (arm_feature(env, ARM_FEATURE_MPU)) {

        /* These are the MPU registers prior to PMSAv6. Any new