Commit 0a8066f0 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170921' into staging 



target-arm queue:
 * more preparatory work for v8M support
 * convert some omap devices away from old_mmio
 * remove out of date ARM ARM section references in comments
 * add the Smartfusion2 board

# gpg: Signature made Thu 21 Sep 2017 17:40:40 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170921: (31 commits)
  msf2: Add Emcraft's Smartfusion2 SOM kit
  msf2: Add Smartfusion2 SoC
  msf2: Add Smartfusion2 SPI controller
  msf2: Microsemi Smartfusion2 System Register block
  msf2: Add Smartfusion2 System timer
  hw/arm/omap2.c: Don't use old_mmio
  hw/i2c/omap_i2c.c: Don't use old_mmio
  hw/timer/omap_gptimer: Don't use old_mmio
  hw/timer/omap_synctimer.c: Don't use old_mmio
  hw/gpio/omap_gpio.c: Don't use old_mmio
  hw/arm/palm.c: Don't use old_mmio for static_ops
  target/arm: Remove out of date ARM ARM section references in A64 decoder
  nvic: Support banked exceptions in acknowledge and complete
  nvic: Make SHCSR banked for v8M
  nvic: Make ICSR banked for v8M
  target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()
  nvic: Handle v8M changes in nvic_exec_prio()
  nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear
  nvic: Implement v8M changes to fixed priority exceptions
  nvic: In escalation to HardFault, support HF not being priority -1
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 9ee660e7 6d262dcb

default-configs/arm-softmmu.mak

+1 −0
Original line number Diff line number Diff line
@@ -129,3 +129,4 @@ CONFIG_ACPI=y 
CONFIG_SMBIOS=y

CONFIG_ASPEED_SOC=y

CONFIG_GPIO_KEY=y

CONFIG_MSF2=y

hw/arm/Makefile.objs

+1 −0
Original line number Diff line number Diff line
@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o 
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o

obj-$(CONFIG_MPS2) += mps2.o

obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o

hw/arm/msf2-soc.c

0 → 100644
+238 −0
Original line number Diff line number Diff line 
/*

 * SmartFusion2 SoC emulation.

 *

 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "qemu/osdep.h"

#include "qapi/error.h"

#include "qemu-common.h"

#include "hw/arm/arm.h"

#include "exec/address-spaces.h"

#include "hw/char/serial.h"

#include "hw/boards.h"

#include "sysemu/block-backend.h"

#include "qemu/cutils.h"

#include "hw/arm/msf2-soc.h"

#include "hw/misc/unimp.h"



#define MSF2_TIMER_BASE       0x40004000

#define MSF2_SYSREG_BASE      0x40038000



#define ENVM_BASE_ADDRESS     0x60000000



#define SRAM_BASE_ADDRESS     0x20000000



#define MSF2_ENVM_MAX_SIZE    (512 * K_BYTE)



/*

 * eSRAM max size is 80k without SECDED(Single error correction and

 * dual error detection) feature and 64k with SECDED.

 * We do not support SECDED now.

 */

#define MSF2_ESRAM_MAX_SIZE       (80 * K_BYTE)



static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };

static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };



static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };

static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };

static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };



static void m2sxxx_soc_initfn(Object *obj)

{

    MSF2State *s = MSF2_SOC(obj);

    int i;



    object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);

    qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());



    object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);

    qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());



    object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);

    qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());



    for (i = 0; i < MSF2_NUM_SPIS; i++) {

        object_initialize(&s->spi[i], sizeof(s->spi[i]),

                          TYPE_MSS_SPI);

        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());

    }

}



static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)

{

    MSF2State *s = MSF2_SOC(dev_soc);

    DeviceState *dev, *armv7m;

    SysBusDevice *busdev;

    Error *err = NULL;

    int i;



    MemoryRegion *system_memory = get_system_memory();

    MemoryRegion *nvm = g_new(MemoryRegion, 1);

    MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);

    MemoryRegion *sram = g_new(MemoryRegion, 1);



    memory_region_init_rom(nvm, NULL, "MSF2.eNVM", s->envm_size,

                           &error_fatal);

    /*

     * On power-on, the eNVM region 0x60000000 is automatically

     * remapped to the Cortex-M3 processor executable region

     * start address (0x0). We do not support remapping other eNVM,

     * eSRAM and DDR regions by guest(via Sysreg) currently.

     */

    memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM",

                             nvm, 0, s->envm_size);



    memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);

    memory_region_add_subregion(system_memory, 0, nvm_alias);



    memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,

                           &error_fatal);

    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);



    armv7m = DEVICE(&s->armv7m);

    qdev_prop_set_uint32(armv7m, "num-irq", 81);

    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);

    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),

                                     "memory", &error_abort);

    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }



    if (!s->m3clk) {

        error_setg(errp, "Invalid m3clk value");

        error_append_hint(errp, "m3clk can not be zero\n");

        return;

    }

    system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;



    for (i = 0; i < MSF2_NUM_UARTS; i++) {

        if (serial_hds[i]) {

            serial_mm_init(get_system_memory(), uart_addr[i], 2,

                           qdev_get_gpio_in(armv7m, uart_irq[i]),

                           115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);

        }

    }



    dev = DEVICE(&s->timer);

    /* APB0 clock is the timer input clock */

    qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);

    object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }

    busdev = SYS_BUS_DEVICE(dev);

    sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);

    sysbus_connect_irq(busdev, 0,

                           qdev_get_gpio_in(armv7m, timer_irq[0]));

    sysbus_connect_irq(busdev, 1,

                           qdev_get_gpio_in(armv7m, timer_irq[1]));



    dev = DEVICE(&s->sysreg);

    qdev_prop_set_uint32(dev, "apb0divisor", s->apb0div);

    qdev_prop_set_uint32(dev, "apb1divisor", s->apb1div);

    object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }

    busdev = SYS_BUS_DEVICE(dev);

    sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);



    for (i = 0; i < MSF2_NUM_SPIS; i++) {

        gchar *bus_name;



        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        if (err != NULL) {

            error_propagate(errp, err);

            return;

        }



        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,

                           qdev_get_gpio_in(armv7m, spi_irq[i]));



        /* Alias controller SPI bus to the SoC itself */

        bus_name = g_strdup_printf("spi%d", i);

        object_property_add_alias(OBJECT(s), bus_name,

                                  OBJECT(&s->spi[i]), "spi",

                                  &error_abort);

        g_free(bus_name);

    }



    /* Below devices are not modelled yet. */

    create_unimplemented_device("i2c_0", 0x40002000, 0x1000);

    create_unimplemented_device("dma", 0x40003000, 0x1000);

    create_unimplemented_device("watchdog", 0x40005000, 0x1000);

    create_unimplemented_device("i2c_1", 0x40012000, 0x1000);

    create_unimplemented_device("gpio", 0x40013000, 0x1000);

    create_unimplemented_device("hs-dma", 0x40014000, 0x1000);

    create_unimplemented_device("can", 0x40015000, 0x1000);

    create_unimplemented_device("rtc", 0x40017000, 0x1000);

    create_unimplemented_device("apb_config", 0x40020000, 0x10000);

    create_unimplemented_device("emac", 0x40041000, 0x1000);

    create_unimplemented_device("usb", 0x40043000, 0x1000);

}



static Property m2sxxx_soc_properties[] = {

    /*

     * part name specifies the type of SmartFusion2 device variant(this

     * property is for information purpose only.

     */

    DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),

    DEFINE_PROP_STRING("part-name", MSF2State, part_name),

    DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),

    DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,

                        MSF2_ESRAM_MAX_SIZE),

    /* Libero GUI shows 100Mhz as default for clocks */

    DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),

    /* default divisors in Libero GUI */

    DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),

    DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),

    DEFINE_PROP_END_OF_LIST(),

};



static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->realize = m2sxxx_soc_realize;

    dc->props = m2sxxx_soc_properties;

}



static const TypeInfo m2sxxx_soc_info = {

    .name          = TYPE_MSF2_SOC,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(MSF2State),

    .instance_init = m2sxxx_soc_initfn,

    .class_init    = m2sxxx_soc_class_init,

};



static void m2sxxx_soc_types(void)

{

    type_register_static(&m2sxxx_soc_info);

}



type_init(m2sxxx_soc_types)

hw/arm/msf2-som.c

0 → 100644
+105 −0
Original line number Diff line number Diff line 
/*

 * SmartFusion2 SOM starter kit(from Emcraft) emulation.

 *

 * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */



#include "qemu/osdep.h"

#include "qapi/error.h"

#include "qemu/error-report.h"

#include "hw/boards.h"

#include "hw/arm/arm.h"

#include "exec/address-spaces.h"

#include "qemu/cutils.h"

#include "hw/arm/msf2-soc.h"

#include "cpu.h"



#define DDR_BASE_ADDRESS      0xA0000000

#define DDR_SIZE              (64 * M_BYTE)



#define M2S010_ENVM_SIZE      (256 * K_BYTE)

#define M2S010_ESRAM_SIZE     (64 * K_BYTE)



static void emcraft_sf2_s2s010_init(MachineState *machine)

{

    DeviceState *dev;

    DeviceState *spi_flash;

    MSF2State *soc;

    MachineClass *mc = MACHINE_GET_CLASS(machine);

    DriveInfo *dinfo = drive_get_next(IF_MTD);

    qemu_irq cs_line;

    SSIBus *spi_bus;

    MemoryRegion *sysmem = get_system_memory();

    MemoryRegion *ddr = g_new(MemoryRegion, 1);



    if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {

        error_report("This board can only be used with CPU %s",

                     mc->default_cpu_type);

    }



    memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,

                           &error_fatal);

    memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);



    dev = qdev_create(NULL, TYPE_MSF2_SOC);

    qdev_prop_set_string(dev, "part-name", "M2S010");

    qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type);



    qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);

    qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);



    /*

     * CPU clock and peripheral clocks(APB0, APB1)are configurable

     * in Libero. CPU clock is divided by APB0 and APB1 divisors for

     * peripherals. Emcraft's SoM kit comes with these settings by default.

     */

    qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);

    qdev_prop_set_uint32(dev, "apb0div", 2);

    qdev_prop_set_uint32(dev, "apb1div", 2);



    object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);



    soc = MSF2_SOC(dev);



    /* Attach SPI flash to SPI0 controller */

    spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");

    spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");

    qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);

    if (dinfo) {

        qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),

                                    &error_fatal);

    }

    qdev_init_nofail(spi_flash);

    cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);

    sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);



    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,

                       soc->envm_size);

}



static void emcraft_sf2_machine_init(MachineClass *mc)

{

    mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";

    mc->init = emcraft_sf2_s2s010_init;

    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");

}



DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)

hw/arm/omap2.c

+37 −12
Original line number Diff line number Diff line
@@ -2087,19 +2087,44 @@ static void omap_sysctl_write(void *opaque, hwaddr addr, 
    }

}



static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,

                                   unsigned size)

{

    switch (size) {

    case 1:

        return omap_sysctl_read8(opaque, addr);

    case 2:

        return omap_badwidth_read32(opaque, addr); /* TODO */

    case 4:

        return omap_sysctl_read(opaque, addr);

    default:

        g_assert_not_reached();

    }

}



static void omap_sysctl_writefn(void *opaque, hwaddr addr,

                                uint64_t value, unsigned size)

{

    switch (size) {

    case 1:

        omap_sysctl_write8(opaque, addr, value);

        break;

    case 2:

        omap_badwidth_write32(opaque, addr, value); /* TODO */

        break;

    case 4:

        omap_sysctl_write(opaque, addr, value);

        break;

    default:

        g_assert_not_reached();

    }

}



static const MemoryRegionOps omap_sysctl_ops = {

    .old_mmio = {

        .read = {

            omap_sysctl_read8,

            omap_badwidth_read32,	/* TODO */

            omap_sysctl_read,

        },

        .write = {

            omap_sysctl_write8,

            omap_badwidth_write32,	/* TODO */

            omap_sysctl_write,

        },

    },

    .read = omap_sysctl_readfn,

    .write = omap_sysctl_writefn,

    .valid.min_access_size = 1,

    .valid.max_access_size = 4,

    .endianness = DEVICE_NATIVE_ENDIAN,

};