Commit 09279d7e authored by Cédric Le Goater's avatar Cédric Le Goater Committed by David Gibson
Browse files

ppc/pnv: change core mask for POWER9 



When addressed by XSCOM, the first core has the 0x20 chiplet ID but
the CPU PIR can start at 0x0.

Signed-off-by: default avatarCédric Le Goater <clg@kaod.org>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 83028a2b

hw/ppc/pnv.c

+2 −2
Original line number Diff line number Diff line
@@ -707,9 +707,9 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 
#define POWER8_CORE_MASK   (0x7e7eull)



/*

 * POWER9 has 24 cores, ids starting at 0x20

 * POWER9 has 24 cores, ids starting at 0x0

 */

#define POWER9_CORE_MASK   (0xffffff00000000ull)

#define POWER9_CORE_MASK   (0xffffffffffffffull)



static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)

{

tests/pnv-xscom-test.c

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = { 
        .xscom_base = 0x000603fc00000000ull,

        .xscom_core_base = 0x0ull,

        .cfam_id    = 0x220d104900008000ull,

        .first_core = 0x20,

        .first_core = 0x0,

    },

#endif

};