Commit 080f2730 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Rebuild hflags for M-profile NVIC 



Continue setting, but not relying upon, env->hflags.

Suggested-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20191023150057.25731-22-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 873be7b6

hw/intc/armv7m_nvic.c

+13 −9
Original line number Diff line number Diff line
@@ -2251,7 +2251,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
            }

        }

        nvic_irq_update(s);

        return MEMTX_OK;

        goto exit_ok;

    case 0x200 ... 0x23f: /* NVIC Set pend */

        /* the special logic in armv7m_nvic_set_pending()

         * is not needed since IRQs are never escalated
@@ -2269,9 +2269,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
            }

        }

        nvic_irq_update(s);

        return MEMTX_OK;

        goto exit_ok;

    case 0x300 ... 0x33f: /* NVIC Active */

        return MEMTX_OK; /* R/O */

        goto exit_ok; /* R/O */

    case 0x400 ... 0x5ef: /* NVIC Priority */

        startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
@@ -2281,10 +2281,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
            }

        }

        nvic_irq_update(s);

        return MEMTX_OK;

        goto exit_ok;

    case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */

        if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {

            return MEMTX_OK;

            goto exit_ok;

        }

        /* fall through */

    case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
@@ -2299,10 +2299,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
            set_prio(s, hdlidx, sbank, newprio);

        }

        nvic_irq_update(s);

        return MEMTX_OK;

        goto exit_ok;

    case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */

        if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {

            return MEMTX_OK;

            goto exit_ok;

        }

        /* All bits are W1C, so construct 32 bit value with 0s in

         * the parts not written by the access size
@@ -2322,15 +2322,19 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, 
             */

            s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);

        }

        return MEMTX_OK;

        goto exit_ok;

    }

    if (size == 4) {

        nvic_writel(s, offset, value, attrs);

        return MEMTX_OK;

        goto exit_ok;

    }

    qemu_log_mask(LOG_GUEST_ERROR,

                  "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);

    /* This is UNPREDICTABLE; treat as RAZ/WI */



 exit_ok:

    /* Ensure any changes made are reflected in the cached hflags.  */

    arm_rebuild_hflags(&s->cpu->env);

    return MEMTX_OK;

}