Commit 0779caeb authored by Arthur Chunqi Li's avatar Arthur Chunqi Li Committed by Gleb Natapov
Browse files

Initialize IA32_FEATURE_CONTROL MSR in reset and migration 



The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs
to clear this MSR when reset vCPU and keep the value of it when
migration. This patch add this feature.

Signed-off-by: default avatarArthur Chunqi Li <yzt356@gmail.com>
Signed-off-by: default avatarGleb Natapov <gleb@redhat.com>
parent f03d07d4

target-i386/cpu.h

+2 −0
Original line number Diff line number Diff line
@@ -301,6 +301,7 @@ 
#define MSR_IA32_APICBASE_BSP           (1<<8)

#define MSR_IA32_APICBASE_ENABLE        (1<<11)

#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)

#define MSR_IA32_FEATURE_CONTROL        0x0000003a

#define MSR_TSC_ADJUST                  0x0000003b

#define MSR_IA32_TSCDEADLINE            0x6e0
@@ -813,6 +814,7 @@ typedef struct CPUX86State { 


    uint64_t mcg_status;

    uint64_t msr_ia32_misc_enable;

    uint64_t msr_ia32_feature_control;



    /* exception/interrupt handling */

    int error_code;

target-i386/kvm.c

+4 −0
Original line number Diff line number Diff line
@@ -1121,6 +1121,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) 
        if (hyperv_vapic_recommended()) {

            kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);

        }

        kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->msr_ia32_feature_control);

    }

    if (env->mcg_cap) {

        int i;
@@ -1345,6 +1346,7 @@ static int kvm_get_msrs(X86CPU *cpu) 
    if (has_msr_misc_enable) {

        msrs[n++].index = MSR_IA32_MISC_ENABLE;

    }

    msrs[n++].index = MSR_IA32_FEATURE_CONTROL;



    if (!env->tsc_valid) {

        msrs[n++].index = MSR_IA32_TSC;
@@ -1443,6 +1445,8 @@ static int kvm_get_msrs(X86CPU *cpu) 
        case MSR_IA32_MISC_ENABLE:

            env->msr_ia32_misc_enable = msrs[i].data;

            break;

        case MSR_IA32_FEATURE_CONTROL:

            env->msr_ia32_feature_control = msrs[i].data;

        default:

            if (msrs[i].index >= MSR_MC0_CTL &&

                msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {

target-i386/machine.c

+22 −0
Original line number Diff line number Diff line
@@ -435,6 +435,14 @@ static bool misc_enable_needed(void *opaque) 
    return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;

}



static bool feature_control_needed(void *opaque)

{

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->msr_ia32_feature_control != 0;

}



static const VMStateDescription vmstate_msr_ia32_misc_enable = {

    .name = "cpu/msr_ia32_misc_enable",

    .version_id = 1,
@@ -446,6 +454,17 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = { 
    }

};



static const VMStateDescription vmstate_msr_ia32_feature_control = {

    .name = "cpu/msr_ia32_feature_control",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



const VMStateDescription vmstate_x86_cpu = {

    .name = "cpu",

    .version_id = 12,
@@ -571,6 +590,9 @@ const VMStateDescription vmstate_x86_cpu = { 
        }, {

            .vmsd = &vmstate_msr_ia32_misc_enable,

            .needed = misc_enable_needed,

        }, {

            .vmsd = &vmstate_msr_ia32_feature_control,

            .needed = feature_control_needed,

        } , {

            /* empty */

        }