Commit 06c1bee8 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/afaerber/tags/prep-for-2.0' into staging 



PReP machine and devices

* Raven PCI host bridge memory fixes (remainder)

# gpg: Signature made Wed 19 Mar 2014 23:35:08 GMT using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg:                 aka "Andreas Färber <afaerber@suse.com>"

* remotes/afaerber/tags/prep-for-2.0:
  raven: Use raven_ for all function prefixes
  raven: Fix PCI bus accesses with size > 1
  raven: Add PCI bus mastering address space
  raven: Set a correct PCI memory region
  raven: Set a correct PCI I/O memory region
  raven: Implement non-contiguous I/O region
  raven: Rename intack region to pci_intack

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents d1a1451c f205da68

hw/pci-host/prep.c

+149 −33
Original line number Diff line number Diff line
@@ -52,15 +52,25 @@ typedef struct RavenPCIState { 
typedef struct PRePPCIState {

    PCIHostState parent_obj;



    MemoryRegion intack;

    qemu_irq irq[PCI_NUM_PINS];

    PCIBus pci_bus;

    AddressSpace pci_io_as;

    MemoryRegion pci_io;

    MemoryRegion pci_io_non_contiguous;

    MemoryRegion pci_memory;

    MemoryRegion pci_intack;

    MemoryRegion bm;

    MemoryRegion bm_ram_alias;

    MemoryRegion bm_pci_memory_alias;

    AddressSpace bm_as;

    RavenPCIState pci_dev;



    int contiguous_map;

} PREPPCIState;



#define BIOS_SIZE (1024 * 1024)



static inline uint32_t PPC_PCIIO_config(hwaddr addr)

static inline uint32_t raven_pci_io_config(hwaddr addr)

{

    int i;
@@ -72,53 +82,133 @@ static inline uint32_t PPC_PCIIO_config(hwaddr addr) 
    return (addr & 0x7ff) |  (i << 11);

}



static void ppc_pci_io_write(void *opaque, hwaddr addr,

static void raven_pci_io_write(void *opaque, hwaddr addr,

                               uint64_t val, unsigned int size)

{

    PREPPCIState *s = opaque;

    PCIHostState *phb = PCI_HOST_BRIDGE(s);

    pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);

    pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);

}



static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,

static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,

                                  unsigned int size)

{

    PREPPCIState *s = opaque;

    PCIHostState *phb = PCI_HOST_BRIDGE(s);

    return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);

    return pci_data_read(phb->bus, raven_pci_io_config(addr), size);

}



static const MemoryRegionOps PPC_PCIIO_ops = {

    .read = ppc_pci_io_read,

    .write = ppc_pci_io_write,

static const MemoryRegionOps raven_pci_io_ops = {

    .read = raven_pci_io_read,

    .write = raven_pci_io_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

};



static uint64_t ppc_intack_read(void *opaque, hwaddr addr,

static uint64_t raven_intack_read(void *opaque, hwaddr addr,

                                  unsigned int size)

{

    return pic_read_irq(isa_pic);

}



static const MemoryRegionOps PPC_intack_ops = {

    .read = ppc_intack_read,

static const MemoryRegionOps raven_intack_ops = {

    .read = raven_intack_read,

    .valid = {

        .max_access_size = 1,

    },

};



static int prep_map_irq(PCIDevice *pci_dev, int irq_num)

static inline hwaddr raven_io_address(PREPPCIState *s,

                                      hwaddr addr)

{

    if (s->contiguous_map == 0) {

        /* 64 KB contiguous space for IOs */

        addr &= 0xFFFF;

    } else {

        /* 8 MB non-contiguous space for IOs */

        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);

    }



    /* FIXME: handle endianness switch */



    return addr;

}



static uint64_t raven_io_read(void *opaque, hwaddr addr,

                              unsigned int size)

{

    PREPPCIState *s = opaque;

    uint8_t buf[4];



    addr = raven_io_address(s, addr);

    address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size);



    if (size == 1) {

        return buf[0];

    } else if (size == 2) {

        return lduw_p(buf);

    } else if (size == 4) {

        return ldl_p(buf);

    } else {

        g_assert_not_reached();

    }

}



static void raven_io_write(void *opaque, hwaddr addr,

                           uint64_t val, unsigned int size)

{

    PREPPCIState *s = opaque;

    uint8_t buf[4];



    addr = raven_io_address(s, addr);



    if (size == 1) {

        buf[0] = val;

    } else if (size == 2) {

        stw_p(buf, val);

    } else if (size == 4) {

        stl_p(buf, val);

    } else {

        g_assert_not_reached();

    }



    address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size);

}



static const MemoryRegionOps raven_io_ops = {

    .read = raven_io_read,

    .write = raven_io_write,

    .endianness = DEVICE_LITTLE_ENDIAN,

    .impl.max_access_size = 4,

    .valid.unaligned = true,

};



static int raven_map_irq(PCIDevice *pci_dev, int irq_num)

{

    return (irq_num + (pci_dev->devfn >> 3)) & 1;

}



static void prep_set_irq(void *opaque, int irq_num, int level)

static void raven_set_irq(void *opaque, int irq_num, int level)

{

    qemu_irq *pic = opaque;



    qemu_set_irq(pic[irq_num] , level);

}



static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,

                                             int devfn)

{

    PREPPCIState *s = opaque;



    return &s->bm_as;

}



static void raven_change_gpio(void *opaque, int n, int level)

{

    PREPPCIState *s = opaque;



    s->contiguous_map = level;

}



static void raven_pcihost_realizefn(DeviceState *d, Error **errp)

{

    SysBusDevice *dev = SYS_BUS_DEVICE(d);
@@ -127,29 +217,30 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp) 
    MemoryRegion *address_space_mem = get_system_memory();

    int i;



    isa_mem_base = 0xc0000000;



    for (i = 0; i < PCI_NUM_PINS; i++) {

        sysbus_init_irq(dev, &s->irq[i]);

    }



    pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);

    qdev_init_gpio_in(d, raven_change_gpio, 1);



    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,

                          "pci-conf-idx", 1);

    sysbus_add_io(dev, 0xcf8, &h->conf_mem);

    sysbus_init_ioports(&h->busdev, 0xcf8, 1);

    pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,

                 PCI_NUM_PINS);



    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s,

                          "pci-conf-data", 1);

    sysbus_add_io(dev, 0xcfc, &h->data_mem);

    sysbus_init_ioports(&h->busdev, 0xcfc, 1);

    memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,

                          "pci-conf-idx", 4);

    memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);



    memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);

    memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,

                          "pci-conf-data", 4);

    memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);



    memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,

                          "pciio", 0x00400000);

    memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);



    memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1);

    memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);

    memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,

                          "pci-intack", 1);

    memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);



    /* TODO Remove once realize propagates to child devices. */

    object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
@@ -160,11 +251,36 @@ static void raven_pcihost_initfn(Object *obj) 
    PCIHostState *h = PCI_HOST_BRIDGE(obj);

    PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);

    MemoryRegion *address_space_mem = get_system_memory();

    MemoryRegion *address_space_io = get_system_io();

    DeviceState *pci_dev;



    memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);

    memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,

                          "pci-io-non-contiguous", 0x00800000);

    /* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */

    memory_region_init(&s->pci_memory, obj, "pci-memory",

                       0x3f000000 + 0xc0000000ULL);

    address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");



    /* CPU address space */

    memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);

    memory_region_add_subregion_overlap(address_space_mem, 0x80000000,

                                        &s->pci_io_non_contiguous, 1);

    memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);

    pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,

                        address_space_mem, address_space_io, 0, TYPE_PCI_BUS);

                        &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);



    /* Bus master address space */

    memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);

    memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",

                             &s->pci_memory, 0,

                             memory_region_size(&s->pci_memory));

    memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",

                             get_system_memory(), 0, 0x80000000);

    memory_region_add_subregion(&s->bm, 0         , &s->bm_pci_memory_alias);

    memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);

    address_space_init(&s->bm_as, &s->bm, "raven-bm");

    pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);



    h->bus = &s->pci_bus;



    object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);

hw/ppc/prep.c

+12 −91
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ typedef struct sysctrl_t { 
    uint8_t state;

    uint8_t syscontrol;

    int contiguous_map;

    qemu_irq contiguous_map_irq;

    int endian;

} sysctrl_t;
@@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 
    case 0x0850:

        /* I/O map type register */

        sysctrl->contiguous_map = val & 0x01;

        qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);

        break;

    default:

        printf("ERROR: unaffected IO port write: %04" PRIx32
@@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 
    return retval;

}



static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,

                                                 hwaddr addr)

{

    if (sysctrl->contiguous_map == 0) {

        /* 64 KB contiguous space for IOs */

        addr &= 0xFFFF;

    } else {

        /* 8 MB non-contiguous space for IOs */

        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);

    }



    return addr;

}



static void PPC_prep_io_writeb (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    cpu_outb(addr, value);

}



static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inb(addr);



    return ret;

}



static void PPC_prep_io_writew (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);

    cpu_outw(addr, value);

}



static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inw(addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);



    return ret;

}



static void PPC_prep_io_writel (void *opaque, hwaddr addr,

                                uint32_t value)

{

    sysctrl_t *sysctrl = opaque;



    addr = prep_IO_address(sysctrl, addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);

    cpu_outl(addr, value);

}



static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)

{

    sysctrl_t *sysctrl = opaque;

    uint32_t ret;



    addr = prep_IO_address(sysctrl, addr);

    ret = cpu_inl(addr);

    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);



    return ret;

}



static const MemoryRegionOps PPC_prep_io_ops = {

    .old_mmio = {

        .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },

        .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

};



#define NVRAM_SIZE        0x2000
@@ -458,13 +375,13 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
    CPUPPCState *env = NULL;

    nvram_t nvram;

    M48t59State *m48t59;

    MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);

    PortioList *port_list = g_new(PortioList, 1);

#if 0

    MemoryRegion *xcsr = g_new(MemoryRegion, 1);

#endif

    int linux_boot, i, nb_nics1;

    MemoryRegion *ram = g_new(MemoryRegion, 1);

    MemoryRegion *vga = g_new(MemoryRegion, 1);

    uint32_t kernel_base, initrd_base;

    long kernel_size, initrd_size;

    DeviceState *dev;
@@ -567,6 +484,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
        fprintf(stderr, "Couldn't create PCI host controller.\n");

        exit(1);

    }

    sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);



    /* PCI -> ISA bridge */

    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
@@ -587,13 +505,16 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) 
    qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */

    qdev_init_nofail(dev);



    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */

    memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl,

                          "ppc-io", 0x00800000);

    memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);



    /* init basic PC hardware */

    pci_vga_init(pci_bus);

    /* Open Hack'Ware hack: PCI BAR#0 is programmed to 0xf0000000.

     * While bios will access framebuffer at 0xf0000000, real physical

     * address is 0xf0000000 + 0xc0000000 (PCI memory base).

     * Alias the wrong memory accesses to the right place.

     */

    memory_region_init_alias(vga, NULL, "vga-alias", pci_address_space(pci),

                             0xf0000000, 0x1000000);

    memory_region_add_subregion_overlap(sysmem, 0xf0000000, vga, 10);



    nb_nics1 = nb_nics;

    if (nb_nics1 > NE2000_NB_MAX)