Commit 0650f1ab authored by Anthony Liguori's avatar Anthony Liguori
Browse files

Add additional CPU flag definitions 



Some x86 CPU definitions that KVM needs

Signed-off-by: default avatarAnthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5625 c046a42c-6fe2-441c-8c8c-71466251a162
parent 2c99f725

target-i386/cpu.h

+8 −1
Original line number Diff line number Diff line
@@ -159,9 +159,11 @@ 
#define HF_MP_MASK           (1 << HF_MP_SHIFT)

#define HF_EM_MASK           (1 << HF_EM_SHIFT)

#define HF_TS_MASK           (1 << HF_TS_SHIFT)

#define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)

#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)

#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)

#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)

#define HF_VM_MASK           (1 << HF_VM_SHIFT)

#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)

#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)

#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
@@ -178,6 +180,9 @@ 
#define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)

#define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)



#define CR0_PE_SHIFT 0

#define CR0_MP_SHIFT 1



#define CR0_PE_MASK  (1 << 0)

#define CR0_MP_MASK  (1 << 1)

#define CR0_EM_MASK  (1 << 2)
@@ -196,7 +201,8 @@ 
#define CR4_PAE_MASK  (1 << 5)

#define CR4_PGE_MASK  (1 << 7)

#define CR4_PCE_MASK  (1 << 8)

#define CR4_OSFXSR_MASK (1 << 9)

#define CR4_OSFXSR_SHIFT 9

#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)

#define CR4_OSXMMEXCPT_MASK  (1 << 10)



#define PG_PRESENT_BIT	0
@@ -229,6 +235,7 @@ 
#define PG_ERROR_RSVD_MASK 0x08

#define PG_ERROR_I_D_MASK  0x10



#define MSR_IA32_TSC                    0x10

#define MSR_IA32_APICBASE               0x1b

#define MSR_IA32_APICBASE_BSP           (1<<8)

#define MSR_IA32_APICBASE_ENABLE        (1<<11)