Commit 05e7e819 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

target-i386: fix set of registers zeroed on reset 



BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
should be (Intel Instruction Set Extensions Programming Reference
319433-015, pages 9-4 and 9-6).  Same for YMM.

XCR0 should be reset to 1.

TSC and TSC_RESET were zeroed already by the memset, remove the explicit
assignments.

Cc: Andreas Faerber <afaerber@suse.de>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent e0723c45

target-i386/cpu.c

+1 −2
Original line number Diff line number Diff line
@@ -2485,8 +2485,7 @@ static void x86_cpu_reset(CPUState *s) 
    cpu_breakpoint_remove_all(s, BP_CPU);

    cpu_watchpoint_remove_all(s, BP_CPU);



    env->tsc_adjust = 0;

    env->tsc = 0;

    env->xcr0 = 1;



#if !defined(CONFIG_USER_ONLY)

    /* We hard-wire the BSP to the first CPU. */

target-i386/cpu.h

+6 −5
Original line number Diff line number Diff line
@@ -797,6 +797,10 @@ typedef struct CPUX86State { 
    target_ulong cr[5]; /* NOTE: cr1 is unused */

    int32_t a20_mask;



    BNDReg bnd_regs[4];

    BNDCSReg bndcs_regs;

    uint64_t msr_bndcfgs;



    /* FPU state */

    unsigned int fpstt; /* top of stack index */

    uint16_t fpus;
@@ -819,6 +823,8 @@ typedef struct CPUX86State { 
    XMMReg xmm_t0;

    MMXReg mmx_t0;



    XMMReg ymmh_regs[CPU_NB_REGS];



    /* sysenter registers */

    uint32_t sysenter_cs;

    target_ulong sysenter_esp;
@@ -928,12 +934,7 @@ typedef struct CPUX86State { 
    uint16_t fpus_vmstate;

    uint16_t fptag_vmstate;

    uint16_t fpregs_format_vmstate;



    uint64_t xstate_bv;

    XMMReg ymmh_regs[CPU_NB_REGS];

    BNDReg bnd_regs[4];

    BNDCSReg bndcs_regs;

    uint64_t msr_bndcfgs;



    uint64_t xcr0;